Method of making an individualization zone of an integrated circuit

A method for making an individualization zone of a microelectronic chip, said chip comprising a first and a second level of electrical tracks, a level of interconnections located between the first and the second levels of electrical tracks and comprising vias to electrically connect electrical tracks of the first level to electrical tracks of the second level, the method comprising, in the individualization zone of the chip:

• providing a stack comprising at least one dielectric layer borne by a substrate with a metal mask layer above the stack, the at least one dielectric layer having a thickness hd and the metal mask layer having a thickness hm and a residual stress σr,
• etching the metal mask layer so as to form line patterns of width l organized according to a predefined arrangement plan, said line patterns to be transferred to the at least one dielectric layer,
• etching the at least one dielectric layer between the line patterns so as to form trenches separated by walls based on the at least one dielectric layer,
• filling the trenches with an electrically conductive material so as to form the electrical tracks of the first level,
• forming vias of the conductor layer according to the predefined arrangement plan, and
• forming the second level of electrical tracks,
• wherein the thicknesses hd and hm, the residual stress σr, and the width l are chosen so that the line patterns and the underlying walls have random oscillations after etching of the at least one dielectric layer, the filling of the trenches being performed so that the electrical tracks of the first level are a function of these random oscillations, and the random oscillations being such that at least some of the vias are not connected to the electrical tracks of the first level.