Semiconductor device package and method for manufacturing the same

A semiconductor device package, comprising:

• a first conductive structure comprising:
• a substrate;
• and
• a first circuit layer disposed on the substrate, wherein the first circuit layer comprises a conductive wiring pattern;
• a multi-layered stress buffering structure disposed on the first conductive structure;
• and
• a second conductive structure disposed over the multi-layered stress buffering structure,
• wherein the buffering structure comprises a first stress buffering layer and a second stress buffering layer arranged on the first stress buffering layer,
• wherein the conductive wiring pattern comprises a via portion including an edge surrounded by the multi-layered stress buffering structure, and a pad portion disposed on the multi-layered stress buffering structure, and a height difference between an upper surface of the pad portion and an upper surface of the multi-layered stress buffering structure is less than or equal to 4 micrometers, and
• wherein the first stress buffering layer surrounds the edge of the via portion, and the second stress buffering layer surrounds the edge of the pad portion.

A method of manufacturing a semiconductor device package, comprising:

• providing a substrate;
• forming a conductive wiring pattern on the substrate;
• forming a stress buffering layer on the substrate to cover the conductive wiring pattern;
• thinning the stress buffering layer to expose an upper surface of the conductive wiring pattern;
• and
• forming a circuit layer on the stress buffering layer and electrically connected to the conductive wiring pattern.