Semiconductor chip stack with locking through vias
AssigneeAdvanced Micro Devices, Inc.
InventorTravis Boraten
Life of this patent
Estimating the term…
Abstract
Various semiconductor chips and chip stack arrangements are disclosed. In one aspect, a semiconductor chip stack is provided that includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first logic layer and a first semiconductor layer on the first logic layer. The first semiconductor layer has plural first through-silicon transistors operable to selectively control the transmission of data from the first semiconductor chip to the second semiconductor chip and has plural first through-silicon vias to convey control signals to the second semiconductor chip.
Claims21
A semiconductor chip stack, comprising:
- a first semiconductor chip;
- a second semiconductor chip stacked on the first semiconductor chip;
- and
- wherein the first semiconductor chip includes a first logic layer and a first semiconductor layer on the first logic layer, the first semiconductor layer having plural first through-silicon transistors operable to selectively control the transmission of data from the first semiconductor chip to the second semiconductor chip and having plural first through-silicon vias to convey control signals to the second semiconductor chip.
An apparatus, comprising:
- a first semiconductor chip operable to have a second semiconductor chip stacked thereon;
- the first semiconductor chip includes a first logic layer and a first semiconductor layer on the first logic layer, the first semiconductor layer having plural first through-silicon transistors operable to selectively control the transmission of data from the first semiconductor chip to the second semiconductor chip and having plural first through-silicon vias to convey control signals to the second semiconductor chip;
- and
- the first semiconductor chip includes an encryption circuit operable to encrypt the data.
A method of manufacturing, comprising:
- stacking a first semiconductor chip on a second semiconductor chip;
- and
- wherein the second semiconductor chip includes a first logic layer and a first semiconductor layer on the first logic layer, the first semiconductor layer having plural first through-silicon transistors operable to selectively control the transmission of data from the second semiconductor chip to the first semiconductor chip and having plural first through-silicon vias to convey control signals to the first semiconductor chip.
Dependencies are inferred from the claim text.