Back to results
US 2022/0028748 A1Published application
Integrated circuit test method and structure thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Wen Liu, Hsien-Wei Chen
Life of this patent
Estimating the term…
Abstract
A device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer.
Claims20
A device comprising:
- a semiconductor die that includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer.
A method, comprising:
- providing an integrated circuit (IC) die, wherein the IC die includes an interconnect layer, a first passivation layer over the interconnect layer, and a conductive pad over the first passivation layer and electrically connecting to the interconnect layer;
- forming a seed layer over the conductive pad;
- forming a sacrificial test pad over the seed layer;
- performing a test to the IC die, wherein the performing of the test includes bringing a flat probe tip into contact with the sacrificial test pad;
- and
- after the performing of the test, removing the sacrificial test pad.
3 more elements
A method, comprising:
- providing an integrated circuit (IC) die, wherein the IC die includes an interconnect layer, a first passivation layer over the interconnect layer, and a conductive pad over the first passivation layer and electrically connecting to the interconnect layer;
- forming a patterned mask over the conductive pad, wherein the patterned mask provides an opening above the conductive pad;
- forming a seed layer over the conductive pad in the opening;
- forming a sacrificial test pad over the seed layer in the opening;
- removing the patterned mask;
- performing a test to the IC die, wherein the performing of the test includes contacting the sacrificial test pad with a probe tip;
- after the performing of the test, removing the sacrificial test pad;
- and
- forming a second passivation layer over the first passivation layer, the conductive pad, and the seed layer.
6 more elements
Dependencies are inferred from the claim text.