Method for making self-aligned post-cut sdb finfet device

A method for making a self-aligned post-cut SDB FinFET device, wherein the method comprises:

• step 1:
• forming a plurality of fin structures located on a substrate and arranged in parallel along a transverse direction, wherein a SiN layer is disposed on the plurality of fin structures, and wherein a first hard mask layer is disposed on the SiN layer;
• step 2:
• depositing a thin oxide layer covering an upper surface of the substrate and sidewalls of the plurality of fin structures;
• step 3:
• depositing an oxide dielectric layer on the SiN layer and fill between the plurality of fin structures, and performing annealing;
• step 4:
• polishing the oxide dielectric layer to expose the SiN layer;
• step 5:
• removing the SiN layer;
• step 6:
• etching back the oxide dielectric layer to expose a height of the plurality of fin structures, wherein the height has a range from 30 to 90 nm;
• step 7:
• depositing a polysilicon layer on exposed part of the plurality of fin structures, depositing a second hard mask layer on the polysilicon layer;
• etching the polysilicon layer and the second hard mask layer to form a plurality of polysilicon-hard mask structures arranged in parallel along a longitudinal direction, and forming sidewalls on sides of the plurality of polysilicon-hard mask structures;
• step 8:
• forming an SiGe region on one of the plurality of fin structures between two adjacent ones of the plurality of polysilicon-hard mask structures;
• forming an SiP region on another of the plurality of fin structures between two other adjacent ones of the plurality of polysilicon-hard mask structures, wherein the SiP region and the SiGe region are configured at two sides of one of the plurality of polysilicon-hard mask structures;
• and
• depositing an ILD layer to fill a space between any two of the plurality polysilicon-hard mask structures;
• step 9:
• removing the second hard mask layer by polishing to expose the polysilicon layer;
• step 10:
• removing the polysilicon layer to form trenches between two adjacent ones of the plurality of polysilicon-hard mask structures;
• step 11:
• filling a high-K dielectric material into the trenches to form high-K metal gates after the polysilicon layer is removed;
• step 12:
• etching back the high-K metal gates;
• step 13:
• depositing a cap layer on the back-etched high-K metal gates and performing planarization on the cap layer;
• step 14:
• etching the plurality of fin structures to form single diffusion break (SDB) trenches;
• and
• step 15:
• forming SiN plugs over the SDB trenches, wherein the SiN plugs are top-sealed hollow structures.