Vertical memory devices and methods of manufacturing the same

A method of manufacturing a vertical memory device, the method comprising:

• forming a circuit pattern on a substrate;
• forming a first insulating interlayer to cover the circuit pattern;
• forming a gate electrode structure including gate electrodes spaced apart from each other on the first insulating interlayer in a vertical direction substantially perpendicular to an upper surface of the substrate, the gate electrode structure being covered by a second insulating interlayer, and each of the gate electrodes including a first metal pattern comprising a low electrical resistance metal and a first metal nitride pattern covering lower and upper surfaces and a sidewall of the first metal pattern;
• forming contact holes extending through the second insulating interlayer in the vertical direction to expose portions of the gate electrodes, respectively;
• and
• forming contact plug structures to fill the contact holes, respectively, each of the contact plug structures including a second metal pattern, a second metal nitride pattern covering a lower surface and a sidewall of the second metal pattern and a second metal silicide pattern covering a lower surface and a sidewall of the second metal nitride pattern,
• wherein at least a portion of the second metal silicide pattern of the contact plug structure is in direct contact with the second insulating interlayer and a first metal pattern of a corresponding one of the gate electrodes, and
• wherein a lower surface of the second metal silicide pattern of the contact plug structure is lower than an upper surface of the first metal nitride pattern in the corresponding one of the gate electrodes.

A method of manufacturing a vertical memory device, the method comprising:

• forming a circuit pattern on a substrate including a cell region and a peripheral region;
• forming a first insulating interlayer to cover the circuit pattern;
• forming a base pattern on a portion of the first insulating interlayer on the cell region of the substrate;
• forming a gate electrode structure including gate electrodes spaced apart from each other on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, the gate electrode structure being covered by a second insulating interlayer on the first insulating interlayer;
• forming first contact holes extending through the second insulating interlayer in the vertical direction to expose portions of the gate electrodes, respectively;
• forming a polysilicon layer on the exposed portions of the gate electrodes, sidewalls of the first contact holes, and the second insulating interlayer;
• forming a second contact hole extending through the first and second insulating interlayers in the vertical direction on the peripheral region of the substrate to expose a portion of the circuit pattern;
• forming a barrier layer on the polysilicon layer, the exposed portion of the circuit pattern, a sidewall of the second contact hole, and the second insulating interlayer;
• transforming a portion of the barrier layer and the polysilicon layer into a metal silicide layer;
• and
• forming first and second metal patterns to fill remaining portions of the first and second contact holes, respectively.