Three-dimensional semiconductor device

A three-dimensional semiconductor device, comprising:

• a semiconductor layer including first, second, third, and fourth well regions doped with first conductivity impurities, the first and second well regions that are adjacent to each other in a first direction, the first and third well regions that are adjacent to each other in a second direction crossing the first direction, and the second and fourth regions that are adjacent to each other in the second direction;
• and
• first, second, third, and fourth cell array structures disposed on the first, second, third, and fourth well regions, respectively;
• wherein each of the first, second, third, and fourth cell array structure comprises:
• a stack structure including a plurality of stacked electrodes stacked in a vertical direction on a top surface of the semiconductor layer;
• and
• a plurality of vertical structures penetrating the stack structure and connected to a corresponding well region,
• wherein the semiconductor layer further includes a separation impurity region doped with second conductivity impurities, and
• wherein the separation impurity region comprises:
• a first region continuously extending along the second direction between the first and second well regions and between the third and fourth well region;
• and
• a second region continuously extending along the first direction between the first and third well regions and between the second and fourth well region.

A three-dimensional semiconductor device, comprising:

• a peripheral logic structure including a peripheral logic circuit integrated on a semiconductor substrate;
• a semiconductor layer on the peripheral logic structure and including first and second well regions and a separation impurity region between the first and second well regions, the first and second well regions doped with first conductivity impurities and the separation impurity region doped with second conductivity impurities;
• and
• a cell array structure provided on each of the first and second well regions of the semiconductor layer,
• wherein the cell array structure comprises:
• a stack structure including a plurality of stacked electrodes stacked in a vertical direction on a top surface of the semiconductor layer;
• and
• a plurality of vertical structures penetrating the stack structure and connected to one of the first and second well regions,
• wherein the separation impurity region surrounds each of the first and second well regions, when viewed in a plan view, and
• wherein the semiconductor layer consists of a single layer.

A three-dimensional semiconductor device, comprising:

• a semiconductor layer including first and second well regions, first and second separation impurity regions spaced apart from each other and disposed between the first and second well regions and a dummy impurity region disposed between the first and second separation impurity regions, the first and second well regions doped with first conductivity impurities and the first and second separation impurity regions doped with second conductivity impurities, and the dummy impurity region doped with the first conductivity impurities;
• first and second cell array structures disposed on the first and second well regions of the semiconductor layer, respectively,
• wherein each of the first and second cell array structures comprises a stack structure including a plurality of electrodes stacked in a vertical direction on a top surface of the semiconductor layer,
• wherein each of the first and second separation impurity regions includes a first region extending along the first direction and a second region extending along a second direction between the first and second well regions and crossing the first region,
• wherein the semiconductor layer consists of a single layer that extends in the first and second directions, and
• wherein the semiconductor layer includes at least two PN junctions formed by the dummy impurity region and the first and second separation impurity regions.