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US 2022/0028476 A1Published application
Repair analysis circuit and memory including the same
AssigneeSK hynix Inc.
InventorHosung CHO
Life of this patent
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Abstract
A memory may include a first repair analysis circuit suitable for storing an input fail address when the input fail address is different from a fail address which is already stored in the first repair analysis circuit, and outputting the input fail address as a first transfer fail address when a storage capacity of the first repair analysis circuit is full; and a second repair analysis circuit suitable for storing the first transfer fail address when the first transfer fail address is different from a fail address which is already stored in the second repair analysis circuit.
Claims5
A memory comprising:
- first to fourth repair analysis circuits;
- and
- a control circuit suitable for:
- controlling the first to fourth repair analysis circuits to store fail addresses of different regions within the memory in a first mode, and
- controlling the first and second repair analysis circuits to store a fail address indicating one region within the memory and controlling the third and fourth repair analysis circuits to store a fail address indicating another region within the memory, in a second mode.
2 more elements
Dependencies are inferred from the claim text.