Methods and apparatus for nand flash memory
AssigneeNEO Semiconductor, Inc.
InventorFu-Chang Hsu
Life of this patent
Estimating the term…
Abstract
Methods and apparatus for memory operations disclosed. In an embodiment, a method is provided for programming multiple-level cells in a memory array. The memory array includes a plurality of planes and each plane includes a plurality of bit lines. The method includes storing multiple data bits in a first group of planes, one data bit per plane. The multiple data bits are stored in bit line capacitances of the first group of planes. The method also includes programming a selected multiple-level cell in a selected plane according to the multiple data bits that are stored in the bit line capacitances of the first group of planes. The selected plane is not one of the first group of planes.
Claims15
A method for programming multiple-level cells in a memory array, wherein the memory array comprises a plurality of planes, and wherein each plane comprises a plurality of bit lines, the method comprising:
- storing multiple data bits in a first group of planes, one data bit per plane, and wherein the multiple data bits are stored in bit line capacitances of the first group of planes;
- and
- programming a selected multiple-level cell in a selected plane according to the multiple data bits that are stored in the bit line capacitances of the first group of planes, and wherein the selected plane is not one of the first group of planes.
A method for programming multiple-level cells in a memory array, wherein the memory array comprises a plurality of banks, and wherein each bank comprises a plurality of multiple-level cells, the method comprising:
- storing first data bits in a first selected bank using single level cell programming;
- reprogramming the first data bits in the first selected bank to a multiple-level cell in a second selected bank using multiple level cell programming during a first reprogramming time interval;
- and
- storing second data bits in a third selected bank during the first reprogramming time interval using single level cell programming.
Dependencies are inferred from the claim text.