Page buffer and operating method thereof
AssigneeSK hynix Inc.
InventorHyung Jin CHOI
Life of this patent
Estimating the term…
Abstract
An electronic device is provided. A page buffer includes at least one data latch, a sensing latch, and a bit line voltage controller. At least one data latch stores a program verification result of a previous program loop among a plurality of program loops and program data to be stored in a memory cell. The sensing latch stores a program verification result of a current program loop among the plurality of program loops. The bit line voltage controller updates the program verification result of the previous program loop which is stored in the at least one data latch to the sensing latch during a program operation of a next program loop of the current program loop among the plurality of program loops.
Claims18
A method of operating a page buffer performing a plurality of program loops each including a program operation and a program verify operation, the method comprising:
- storing a program verification result of a previous program loop among the plurality of program loops in a data latch;
- storing a program verification result of a current program loop among the plurality of program loops in a sensing latch;
- and
- updating the program verification result of the previous program loop, which is stored in the data latch, to the sensing latch during a program operation of a next program loop among the plurality of program loops.
A page buffer, comprising:
- at least one data latch storing a program verification result of a previous program loop among a plurality of program loops and program data to be stored in a memory cell;
- a sensing latch storing a program verification result of a current program loop subsequent to the previous program loop among the plurality of program loops;
- and
- a bit line voltage controller updating the program verification result of the previous program loop, which is stored in the at least one data latch, to the sensing latch during a program operation of a next program loop subsequent to the current program loop among the plurality of program loops.
A page buffer, comprising:
- at least one data latch storing a program verification result of a first program loop, among the first program loop, a second program loop, and a third program loop which are sequentially performed, and program data to be stored in a memory cell;
- a sensing latch storing a program verification result of the second program loop;
- and
- a bit line voltage controller updating the program verification result of the first program loop, which is stored in the at least one data latch, to the sensing latch during a program operation of the third program loop.
A circuitry comprising:
- a first latch and a second latch that are coupled to a bit line;
- and
- a control logic configured to sequentially perform first to third program loops to store, in a memory cell coupled to the bit line, data latched in the second latch,
- wherein the control logic is configured to control the second latch to further latch a first program verification result of the first program loop and the first latch to latch a second program verification result of the second program loop, and
- wherein, during the third program loop, the control logic is configured to:
- control the first latch to further latch the first program verification result from the second latch,
- set up the bit line based on the first program verification result and the second program verification result from the first latch, and
- control the second latch to further latch the second program verification result from the first latch.
Dependencies are inferred from the claim text.