Memory device and operating method thereof
AssigneeSK hynix Inc.
InventorsJae Hyeon SHIN, Gwi Han KO, Sung Hun KIM, Gwan PARK, Hyun Soo LEE
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Abstract
A memory device may include a first sub-block and a second sub-block each including a plurality of select transistors and a plurality of memory cells, a peripheral circuit performing a read operation on data stored in the first sub-block, and a control logic controlling the peripheral circuit to turn on the plurality of select transistors included in each of the first and second sub-blocks and apply a read voltage to a selected word line among a plurality of word lines.
Claims20
A memory device, comprising:
- a first sub-block including a plurality of first select transistors and a plurality of first memory cells;
- a second sub-block coupled to the first sub-block through a plurality of word lines and including a plurality of second select transistors and a plurality of second memory cells;
- a peripheral circuit performing a read operation on data stored in the first sub-block or the second sub-block;
- and
- a control logic controlling the peripheral circuit to apply a read voltage to a selected word line among the plurality of word lines,
- wherein, when the read operation is performed on the first sub-block, the control logic controls the peripheral circuit to:
- turn on the plurality of first select transistors and the plurality of second select transistors,
- increase a voltage level of the plurality of word lines from a first level to a second level,
- turn off the plurality of second select transistors when the voltage level of the plurality of word lines reaches the second level, and
- increase the voltage level of the plurality of word lines from the second level to a third level.
A method of operating a memory device including a first sub-block including a plurality of first select transistors and a plurality of first memory cells, and a second sub-block coupled to the first sub-block through a plurality of word lines and including a plurality of second select transistors and a plurality of second memory cells, the memory device performing a read operation on the first sub-block, the method comprising:
- turning on the plurality of first select transistors and the plurality of second select transistors;
- increasing a voltage level of the plurality of word lines from a first level to a second level;
- turning off the plurality of second select transistors;
- and
- increasing the voltage level of the plurality of word lines from the second level to a third level.
A memory device, comprising:
- a first sub-block including a plurality of first select transistors and a plurality of first memory cells;
- a second sub-block coupled to the first sub-block through a plurality of word lines and including a plurality of second select transistors and a plurality of second memory cells;
- and
- a peripheral circuit performing a read operation on data stored in the first sub-block or the second sub-block,
- wherein, in performing the read operation, the peripheral circuit turns on the plurality of first select transistors and the plurality of second select transistors, increases a voltage level of the plurality of word lines in stepwise increments including at least two stepped increases, and turns off the plurality of second select transistors when the voltage level of the plurality of word lines reaches a target voltage level.
Dependencies are inferred from the claim text.