Non-volatile memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsYOUN-YEOL LEE, WOOK-GHEE HAHN
Life of this patent
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Abstract
A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.
Claims12
A non-volatile memory, comprising:
- an upper semiconductor layer vertically stacked on a lower semiconductor layer, wherein the upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region,
- the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group,
- wherein the bypass circuit includes a transistor including a first source/drain region and a second source/drain region, and
- the non-volatile memory device further comprises:
- a first contact plug extending from the first source/drain region through the separation region to connect the first bit line;
- and
- a second contact plug extending from the second source/drain region through the separation region to connect the second bit line,
- wherein the transistor further includes a gate, and
- the non-volatile memory device further comprises:
- a control logic that generates a connection control signal applied to the gate, wherein the bypass circuit selectively connects the first bit line with the second bit line in response to the connection control signal.
A non-volatile memory, comprising:
- an upper semiconductor layer vertically stacked on a lower semiconductor layer, wherein the upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, wherein the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group;
- a lower substrate underlying the lower semiconductor layer;
- a first upper substrate and a second upper substrate respectively disposed on an upper surface of the lower semiconductor layer, wherein the separation region extends between the first upper substrate and the second upper substrate;
- a first vertical structure disposed on the first upper substrate and including memory cells of the first memory group and a second vertical structure disposed on the second upper substrate and including memory cells of the second memory group,
- wherein the first bit lines including the first bit line are disposed on the first vertical structure and extend in the first horizontal direction,
- the second bit lines including the second bit line are disposed on the second vertical structure and extend in the first horizontal direction, and
- the first bit lines and second bit lines are electrically insulated from one another by the separation region.
3-13. (canceled)
A three-dimensional (3D), non-volatile memory, comprising:
- a control logic that generates a connection control signal;
- an upper semiconductor layer vertically stacked on a lower semiconductor layer,
- wherein the upper semiconductor layer includes a first memory group electrically isolated from a second memory group by a separation region, the first memory group including a first set of tiles including a first tile incorporating a first memory cell array, and the second memory group including a second set of tiles including a second tile incorporating a second memory cell array, and
- the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region, wherein the bypass circuit is configured to selectively connect a first bit line of the first tile with a second bit line of the second tile in response to the connection control signal.
Dependencies are inferred from the claim text.