Nonvolatile memory apparatus performing consecutive access operations and an operation method of the nonvolatile memory apparatus
AssigneeSK hynix Inc.
InventorMin Chul SHIN
Life of this patent
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Abstract
A nonvolatile memory apparatus includes a memory cell array and a memory control circuit. The memory cell array includes a plurality of sub arrays each including a plurality of memory cells coupled to a plurality of bit lines. The memory control circuit sequentially couples thereto, based on a single read command signal, at least a single bit line disposed on the respective sub arrays to sequentially access a memory cell coupled to the at least single bit line.
Claims19
A nonvolatile memory apparatus comprising:
- a memory cell array including a plurality of sub arrays each including a plurality of memory cells coupled to a plurality of bit lines;
- and
- a memory control circuit configured to sequentially couple to, based on a single read command signal, at least one bit line disposed on the respective sub arrays to sequentially read data from a memory cell coupled to the at least one bit line.
An operating method of a nonvolatile memory apparatus, the operating method comprising:
- charging a global bit line and a local bit line coupled to the global bit line based on a single read command signal;
- coupling the local bit line to a first bit line disposed on a first sub array and reading data from a memory cell coupled to the first bit line;
- and
- coupling the local bit line to a second bit line disposed on a second sub array and reading data from a memory cell coupled to the second bit line.
A nonvolatile memory apparatus comprising:
- a controller configured to generate a column address signal based on an address signal, and sequentially enable a plurality of different local column selecting signals while a global column selecting signal is enabled on a basis of the column address signal;
- a column selecting circuit configured to select a local bit line to be coupled to a selected global bit line on a basis of the global column selecting signal and couple at least one bit line on a respective plurality of sub arrays to the selected local bit line based on the plurality of local column selecting signals;
- a column control circuit configured to provide a column access voltage to the selected global bit line based on a read command signal;
- and
- a plurality of sense amplifiers respectively coupled to a plurality of memory cells coupled to the at least one bit line on the respective sub arrays and configured to read data from the plurality of memory cells to generate output data.
Dependencies are inferred from the claim text.