Storage and offset memory cells

An apparatus, comprising:

• a plurality of sense amplifiers, wherein each sense amplifier is coupled to a respective plurality of storage memory cells via a respective first digit line and a respective plurality of offset memory cells via a respective second digit line,
• wherein respective voltages held capacitively by the plurality of storage memory cells correspond to data values,
• wherein respective voltages held capacitively by the plurality of offset memory cells do not correspond to data values, and
• wherein the plurality of offset memory cells have a cumulative capacitance that is approximately equal to a capacitance of the first digit line.

A method, comprising:

• selectively coupling a subset of memory cells of a first plurality of memory cells couplable to a first conductive line of a memory array,
• wherein respective voltages held capacitively by the subset of memory cells do not correspond to data values, and
• wherein a cumulative capacitance of the subset of memory cells is approximately equal to a capacitance of a second conductive line of the memory array;
• sensing, using a sense amplifier coupled to the first and second conductive lines, a respective data value stored by each of a second plurality of memory cells coupled to the second conductive line;
• and
• offsetting a voltage differential of the sense amplifier with a cumulative voltage held capacitively by the subset of memory cells, wherein offsetting the voltage differential comprises:
• charging the subset of memory cells to the cumulative voltage;
• capacitively holding the cumulative voltage by the subset of memory cells;
• and
• concurrent with sensing the data value, discharging the cumulative voltage from the subset of memory cells.

An apparatus, comprising:

• an array of memory cells, formed on a CMOS layer, comprising:
• a plurality of storage memory cells coupled to a first conductive line, wherein respective voltages held capacitively by the plurality of storage memory cells correspond to data values;
• and
• a plurality of offset memory cells coupled to a plurality of word lines and selectively couplable to a second conductive line via activation of a plurality of vertical pillar access devices,
• wherein the plurality of vertical pillar access devices are activated by application of a signal to the plurality of word lines,
• wherein respective voltages held capacitively by the plurality of offset memory cells do not correspond to data values, and
• wherein a cumulative capacitance of the plurality of offset memory cells offsets a capacitance of the first conductive line;
• and
• a sense amplifier, formed in the CMOS layer, coupled to the first and second conductive lines.