Data receiving devices, memory devices having the same, and operating methods thereof

A memory device comprising:

• a memory cell array having a plurality of memory cells at intersections of a plurality of word lines and a plurality of bit lines;
• a row decoder configured to select any one of the plurality of word lines in response to a row address;
• a bit line sense amplifying circuit configured to sense and to amplify data from selected ones of the plurality of memory cells during a reading operation;
• a column driver configured to select bit lines among the plurality of bit lines in response to a column address;
• and
• a data input/output device configured to receive data from the bit line sense amplifying circuit during the reading operation, and to receive input data from data pads during a writing operation,
• wherein the data input/output device includes at least one respective data input sense amplifier connected to each of the data pads, and
• wherein the at least one respective data input sense amplifier includes a first stage that is configured to output differential signals by amplifying the input data using a reference voltage selected in response to previous data, and a second stage that is configured to latch the input data by amplifying the differential signals.