# US 2022/0028433 A1 · Biasing electronic components using adjustable circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0028433 A1 - Document ID: US20220028433A1 - Status: Published application - Kind: A1 - Application number: 16/934,213 - Filed: 2020-07-21 - Published: 2022-01-27 - Earliest claimed: 2020-07-21 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: John David Porter; Suryanarayana B. Tatapudi - Web page: https://patentgrep.com/patent/US20220028433A1 ## CPC - G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs} - G11C 29/028: {with adaption or trimming of parameters} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 7/08: Control thereof - G11C 29/021: {in voltage or current generators} - G11C 29/026: {in sense amplifiers} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Embodiments relate to improving the biasing of active electronic components such as, for example, sense amplifiers. Embodiments include an adjustable bias signal generator that receives a reference signal as an input and generates a corresponding bias signal as an output. The adjustable bias signal generator may comprise a voltage driver and capacitor divider circuitry. In some embodiments, the capacitor divider circuitry is configurable by selecting specific capacitor dividers using a digital code. In other embodiments, the voltage driver is adjustable by applying different trim settings to tune the output of the voltage driver. The voltage driver may be temperature compensated by multiplexing different trim settings that correspond to different temperatures. ## Claims ### Claim 1 An electronic device comprising: a reference signal generator configured to generate a reference signal for a memory array; an adjustable bias signal generator configured to receive the reference signal as an input and generate a corresponding bias signal as an output, the adjustable bias signal generator comprising a voltage driver and capacitor divider circuitry, wherein the voltage driver of the adjustable bias signal generator comprises a fixed voltage driver, wherein the capacitor divider circuitry of the adjustable bias signal generator comprises a set of capacitor dividers, and wherein the adjustable bias signal generator is adjusted by selecting a capacitor divider among the set of capacitor dividers; and a sense amplifier array of the memory array, the sense amplifier array configured to be biased according to the corresponding bias signal. ### Claim 2 (canceled) ### Claim 3 (depends on 1) The electronic device of claim 1, wherein each capacitor divider corresponds to a respective digital code. ### Claim 4 (depends on 1) The electronic device of claim 1, further comprising a state machine configured to select the capacitor divider by sequentially activating capacitor dividers and comparing an output of each activated capacitor divider to the reference signal. ### Claim 5 (depends on 1) The electronic device of claim 1, further comprising a state machine configured to select the capacitor divider according to a predetermined schedule to update the capacitor divider. ### Claim 6 (depends on 1) The electronic device of claim 1, wherein a first capacitor divider is selected for a high reference signal for a high bias condition and a second capacitor divider is selected for a low reference signal for a low bias condition. ### Claim 7 (depends on 1) The electronic device of claim 1, further comprising a multiplexor configured to receive a digital code for a high reference signal and a digital code for a low reference signal. ### Claim 8 (depends on 7) The electronic device of claim 7, wherein the adjustable bias signal generator comprises an enable switch to set the sense amplifier array in a standby mode. ### Claim 9 (depends on 1) The electronic device of claim 1, wherein the voltage driver of the adjustable bias signal generator comprises at least one digital voltage driver, wherein the capacitor divider circuitry of the adjustable bias signal generator comprises fixed capacitor divider circuitry, wherein the adjustable bias signal generator is adjusted by trimming the at least one digital voltage driver to match a voltage of the bias signal voltage with a voltage of the reference signal. ### Claim 10 (depends on 9) The electronic device of claim 9, wherein the reference signal comprises a high reference signal and a low reference signal to bias the sense amplifier array at different bias levels, wherein the at least one digital voltage driver is configured to drive a first capacitor divider arrangement in response to the high reference signal and drive a second capacitor divider arrangement in response to the low reference signal. ### Claim 11 (depends on 10) The electronic device of claim 10, wherein each of a first digital voltage driver and a second digital voltage driver comprise a plurality of trim settings corresponding to different temperatures. ### Claim 12 (depends on 1) The electronic device of claim 1, wherein the voltage driver comprises at least one of a bandgap reference voltage generator or a current mirror having a resistor controlling a current of the reference signal. ### Claim 13 A method comprising: receiving, by an adjustable bias signal generator, a reference signal as an input; generating, by the adjustable bias signal generator, a corresponding bias signal as an output by using a fixed voltage generator, wherein the output of the fixed voltage generator is coupled to a capacitor divider that is selected among a set of capacitor dividers according to a digital code; and biasing a sense amplifier array of a memory array according to the bias signal, the bias signal being generated at the output of the selected capacitor divider. ### Claim 14 (depends on 13) The method of claim 13, further comprising: selecting the capacitor divider by sequentially activating capacitor dividers; and comparing an output of each activated capacitor divider to the reference signal. ### Claim 15 (depends on 14) The method of claim 14, wherein a state machine performs the selecting and the comparing according to a predetermined schedule to update the capacitor divider. ### Claim 16 (depends on 13) The method of claim 13, wherein a first capacitor divider is selected for a high reference signal for a high bias condition and a second capacitor divider is selected for a low reference signal for a low bias condition. ### Claim 17 (depends on 13) The method of claim 13, further comprising: receiving, by a multiplexor, a digital code for a high reference signal and a digital code for a low reference signal. ### Claim 18 A method comprising: receiving, by an adjustable bias signal, a reference signal as an input; generating, by a trimmed digital driver, an intermediate voltage output according to the reference signal; generating a bias signal at the output of a fixed capacitor divider according to the intermediate voltage output; and biasing a sense amplifier array of a memory array according to the bias signal, wherein the reference signal comprises a high reference signal and a low reference signal to bias the sense amplifier array at difference bias levels, wherein the trimmed digital voltage driver is configured to drive a first capacitor divider arrangement in response to the high reference signal and drive a second capacitor divider arrangement in response to the low reference signal. ### Claim 19 (canceled) ### Claim 20 (depends on 18) The method of claim 18, wherein each of the trimmed digital voltage driver comprises a plurality of trim settings corresponding to different temperatures, the trim settings being multiplexed.