Image processing device

An image processing device comprising circuit chips, a first external circuit, and a second external circuit, each of the circuit chips being a system on a chip (SoC), and the circuit chips being configured to cooperate and including a first SoC and a second SoC, wherein:

• the first SoC includes:
• a first processor cooperation area including:
• a first processor;
• and
• a first transceiver;
• and
• a first image circuit cooperation area including:
• a data splitter configured to divide input image data into multiple input parts including a first input part and a second input part;
• a first image processing circuit coupled to the data splitter, and configured to receive and process the first input part to generate a first output part of multiple output parts of output image data;
• and
• a transmitter coupled to the data splitter, and configured to receive the second input part to forward the second input part to the second SoC via the first external circuit;
• the first external circuit is set outside any of the first SoC and the second SoC;
• the second external circuit is set outside any of the first SoC and the second SoC;
• the second SoC includes:
• a second processor cooperation area including:
• a second transceiver;
• and
• a second processor, wherein the second processor is configured to cooperate with the first processor through the second transceiver, the second external circuit, and the first transceiver;
• and
• a second image circuit cooperation area including:
• a receiver configured to receive the second part via the first external circuit;
• and
• a second image processing circuit coupled to the receiver, and configured to receive and process the second input part to generate a second output part of the multiple output parts of the output image data;
• and
• a combination of the first output part and the second output part is characterized by an output image size and an output frame rate, the output image size and the output frame rate jointly determine a data amount per unit of time, and the data amount per unit of time exceeds a processing capability of the first image processing circuit per unit of time and exceeds a processing capability of the second image processing circuit per unit of time.