Neural network accelerator
AssigneeEdgecortix Pte. Ltd.
InventorsNikolay Nez, Antonio Tomas Nevado Vilchez, Hamid Reza Zohouri, Mikhail Volkov, Oleg Khavin, Sakyasingha Dasgupta
Life of this patent
Estimating the term…
Abstract
Neural network inference may be performed by an apparatus or integrated circuit configured to perform mathematical operations on activation data stored in an activation data memory and weight values stored in a weight memory, to store values resulting from the mathematical operations onto an accumulation memory, to perform activation operations on the values stored in the accumulation memory, to store resulting activation data onto the activation data memory, and to perform inference of a neural network by feeding and synchronizing instructions from an external memory.
Claims20
An apparatus comprising:
- an activation data memory;
- a data loading module configured to load activation data from an external memory onto the activation data memory;
- a data storing module configured to store activation data from the activation data memory onto the external memory;
- a weight memory;
- a weight loading module configured to load weight values from an external memory onto the weight memory;
- an accumulation memory;
- a plurality of convolution modules configured to perform mathematical operations on the activation data stored in the activation data memory and the weight values stored in the weight memory, and to store values resulting from the mathematical operations onto the accumulation memory;
- a plurality of activation modules configured to perform activation operations on the values stored in the accumulation memory, and to store resulting activation data onto the activation data memory;
- and
- an instruction module configured to feed and synchronize instructions from the external memory to the data loading module, the data storing module, the weight loading module, the plurality of convolution modules, and the plurality of activation modules, to perform inference of a convolutional neural network.
An integrated circuit comprising:
- a plurality of convolution modules configured to perform mathematical operations on activation data stored in an activation data memory and weight values stored in a weight memory, and to store values resulting from the mathematical operations onto an accumulation memory;
- a plurality of activation modules configured to perform activation operations on the values stored in the accumulation memory, and to store resulting activation data onto the activation data memory;
- and
- an instruction module configured to perform inference of a neural network by feeding and synchronizing instructions from an external memory to the plurality of convolution modules and the plurality of activation modules.
An integrated circuit comprising:
- an on-chip memory;
- and
- a plurality of logic gates, the plurality of logic gates arranged in groups including
- a plurality of first groups configured to perform mathematical operations on activation data and weight values stored in the on-chip memory, and to store values resulting from the mathematical operations onto the on-chip memory;
- a plurality of second groups configured to perform activation operations on the resulting values stored in the on-chip memory, and to store resulting activation data onto the on-chip memory;
- and
- a third group configured to perform inference of a neural network by feeding and synchronizing instructions from an external memory to the plurality of first groups and the plurality of second groups.
Dependencies are inferred from the claim text.