Microprocessor that conditions store-to-load forwarding on circumstances associated with a translation context update
AssigneeVentana Micro Systems Inc.
InventorJohn G. Favor
Life of this patent
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Abstract
A processor is disclosed that mitigates side channel attacks that exploit speculative store-to-load forwarding. The processor includes logic that conditions store-to-load forwarding of uncommitted store data in the store queue from an uncommitted store instruction to the load instruction upon circumstances associated with a translation context (TC) change or update. The TC comprises an address space identifier (ASID), a virtual machine identifier (VMID), a privilege mode (PM) or a combination of two or more of the ASID, VMID and PM or a derivative thereof. The logic is embedded or associated with any of several structures, such as a store queue (SQ), a memory dependence predictor (MDP), or a reorder buffer (ROB).
Claims22
A method for mitigating side channel attacks that exploit store-to-load forwarding in a processor, the method comprising:
- recording a translation context (TC) applicable to instructions dispatched from a decode unit of the processor;
- detecting updates and/or changes to the TC;
- conditioning store-to-load forwarding from an uncommitted store instruction to a load instruction upon circumstances associated with the TC update and/or change;
- wherein a TC comprises an address space identifier (ASID), a virtual machine identifier (VMID), a privilege mode (PM) or a translation regime (TR), a combination of two or more of the ASID, VMID, and TR or PM, or a hash and/or subset of the ASID, VMID, and/or TR or PM.
A processor that mitigates side channel attacks that exploit speculative store-to-load forwarding in a processor, the processor comprising:
- a store queue (SQ) that holds uncommitted store data of store instructions until the store data is written to a data cache;
- store-to-load forwarding logic that conditions store-to-load forwarding of uncommitted store data in the store queue from an uncommitted store instruction to the load instruction upon circumstances associated with a TC update or change;
- wherein a TC comprises an ASID, VMID, PM or TR, a combination of two or more of the ASID, VMID, and TR or PM, or a hash and/or subset of the ASID, VMID, and/or TR or PM.
A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a processor for mitigating side channel attacks, the processor comprising:
- an SQ that holds uncommitted store data of store instructions until the store data is written to the data cache;
- store-to-load forwarding logic that conditions store-to-load forwarding of uncommitted store data in the SQ from an uncommitted store instruction to the load instruction upon circumstances associated with a TC update;
- wherein a TC comprises an ASID, VMID, PM or TR, a combination of two or more of the ASID, VMID, and TR or PM, or a hash and/or subset of the ASID, VMID, and/or TR or PM.
A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a processor for mitigating side channel attacks, the processor comprising:
- a store dependence predictor that predicts whether store data is or will be available and forwardable to a load instruction, wherein the store dependence predictor:
- is accessible using an identifier and TC of a load instruction;
- and
- generates a signal that reflects said prediction of whether store data is available and forwardable to the load instruction;
- wherein a TC comprises an ASID, VMID, PM or TR, a combination of two or more of the ASID, VMID, and TR or PM, or a hash and/or subset of the ASID, VMID, and/or TR or PM.
Dependencies are inferred from the claim text.