Microprocessor that prevents store-to-load forwarding between different translation contexts

A method of mitigating side channel attacks (SCAs) that exploit store-to-load forwarding operations on a pipelined, speculative out-of-order execution processor, the method comprising:

• dispatching instructions in a pipeline of the processor;
• associating program order ordinals with each load instruction and each store instruction advancing between decode and execution stages of the pipeline;
• tracking program order ordinals for each instruction in a set of one or more most recent instructions that caused a TC change;
• decoding and issuing a load instruction;
• identifying a candidate prior uncommitted store instruction from which to potentially forward store data to the load instruction;
• comparing the program order ordinals of the load instruction and the candidate prior uncommitted store instruction with the program order ordinal of each instruction of the set of one or more recent TC change-causing instructions;
• when there is at least one TC change-causing instruction between the candidate prior uncommitted store instruction and the load instruction, as determined by the comparison of program order ordinals, preventing store-to-load forwarding from the candidate prior uncommitted store instruction to the load instruction;
• and
• wherein a TC comprises an address space identifier (ASID), a virtual machine identifier (VMID), a privilege mode (PM) or a translation regime (TR), a combination of two or more of the ASID, VMID, and TR or PM, or a hash and/or subset of the ASID, VMID, and/or TR or PM.

A processor that mitigates against side channel attacks (SCAs) using store-to-load forwarding operations, the processor comprising:

• a pipeline of units that fetch, decode, and execute instructions, including a decode unit that decodes and dispatches instructions and a load-store unit that executes load and store instructions;
• translation-context monitoring logic that detects an event that updates the TC from a first TC to a second TC;
• and
• store-to-load forwarding logic that, for at least a subset of TC updates where the second TC is different from the first TC, responsively prevents store-to-load forwarding for load instructions dispatched in the second TC that are dependent on store instructions dispatched in the first TC;
• wherein a TC comprises an ASID, a VMID, a PM or a TR, a combination of two or more of the ASID, VMID, and TR or PM, or a hash and/or subset of the ASID, VMID, and/or TR or PM.

A non-transitory computer-readable medium having instructions stored thereon that are capable causing or configuring a pipelined, speculative out-of-order execution processor that mitigates side channel attacks (SCAs) that exploit store-to-load forwarding operations, the processor comprising:

• a pipeline of units that fetch, decode, and execute instructions, including a decode unit that decodes and dispatches instructions and a load-store unit that executes load and store instructions;
• translation-context monitoring logic that detects an instruction that updates the TC from a first TC to a second TC;
• store-to-load forwarding logic that, for at least a subset of TC updates where the second TC is different from the first TC, responsively prevents store-to-load forwarding for load instructions dispatched in the second TC that are dependent on the first TC;
• wherein a TC comprises an ASID, VMID, PM or TR, a combination of two or more of the ASID, VMID, and TR or PM, or a hash and/or subset of the ASID, VMID, and/or TR or PM.