Device and method for controlling memory access in parallel processing system

A memory access controlling method in a parallel processing system, comprising:

• receiving an optical signal comprising a memory access frame from an optical circuit switch (OCS) through an optical transceiver;
• performing, by a memory access controller, a scheduling operation and a memory access control operation based on the memory access frame, and transmitting a memory processing instruction and memory address information to a memory controller;
• performing, by the memory controller, a memory access operation comprising at least one of memory data read or memory data write based on the memory processing instruction and the memory address information;
• and
• transmitting resultant data obtained by the memory access operation to the OCS through the optical transceiver,
• wherein the memory access controller comprises a plurality of header processors, and is configured to control memory processing instructions to be performed in sequential order based on connection information between each of the header processors and a target memory.