US 2022/0027288 A1 · TECHNOLOGIES FOR LOW-LATENCY CRYPTOGRAPHY FOR PROCESSOR-ACCELERATOR COMMUNICATION

Abstract

Technologies for secure data transfer include a computing device having a processor, an accelerator, and a security engine, such as a direct memory access (DMA) engine or a memory-mapped I/O (MMIO) engine. The computing device initializes the security engine with an initialization vector and a secret key. During initialization, the security engine pre-fills block cipher pipelines and pre-computes hash subkeys. After initialization, the processor initiates a data transfer, such as a DMA transaction or an MMIO request, between the processor and the accelerator. The security engine performs an authenticated cryptographic operation for the data transfer operation. The authenticated cryptographic operation may be AES-GCM authenticated encryption or authenticated decryption. The security engine may perform encryption or decryption using multiple block cipher pipelines. The security engine may calculate an authentication tag using multiple Galois field multipliers. Other embodiments are described and claimed.

Claims20

Dependent claims

An apparatus comprising:

one or more processors coupled to or host one or more of a security engine circuitry, an initialization manager circuitry, and a transfer manager circuitry, wherein:
the initialization manager circuitry to initialize the security engine circuitry with an initialization vector and a secret key;
the transfer manager circuitry to initiate a data transfer operation between a trusted execution environment and an accelerator device in response to initialization of the security engine circuitry, wherein initiating the data transfer operation includes initiating a memory-mapped input/output (I/O) operation with an input data block;
and
the security engine circuitry to perform an authenticated cryptographic operation associated with the data transfer operation.

2 more elements

A method comprising:

initializing, by an initialization manager circuitry, a security engine circuitry with an initialization vector and a secret key, wherein the security engine circuitry is coupled to one or more processors further coupled to the initialization manager circuitry and a transfer manager circuitry;
initiating, by the transfer manager circuitry, a data transfer operation between a trusted execution environment and an accelerator device in response to initialization of the security engine circuitry, wherein initiating the data transfer operation includes initiating a memory-mapped input/output (I/O) operation with an input data block;
and
performing, by the security engine circuitry, an authenticated cryptographic operation associated with the data transfer operation.

1 more element

A computer-readable medium having stored thereon instructions which, when executed, cause one or more processors to facilitate operations comprising:

initializing, by an initialization manager circuitry, a security engine circuitry with an initialization vector and a secret key, wherein the security engine circuitry is coupled to the one or more processors further coupled to the initialization manager circuitry and a transfer manager circuitry;
initiating, by the transfer manager circuitry, a data transfer operation between a trusted execution environment and an accelerator device in response to initialization of the security engine circuitry, wherein initiating the data transfer operation includes initiating a memory-mapped input/output (I/O) operation with an input data block;
and
performing, by the security engine circuitry, an authenticated cryptographic operation associated with the data transfer operation.

1 more element

Dependencies are inferred from the claim text.

Technologies for low-latency cryptography for processor-accelerator communication

Life of this patent

Technologies for low-latency cryptography for processor-accelerator communication

Life of this patent

Abstract

Claims20