Semiconductor device and cache control method
AssigneeFujitsu Limited
InventorYASUNOBU AKIZUKI
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a plurality of cores, each including an instruction execution circuit and a first cache, and a second cache shared by the plurality of cores. In each of the cores, a number of completed instructions for each type of the instructions executed by the instruction execution circuit are counted, and an execution frequency for each type of instructions are calculated. Based on the execution frequencies, a cache line size preferable for use in the first cache in the core is selected. Based on the selected preferable cache line sizes for the cores, a cache line size used in the first caches and the second cache is determined.
Claims16
A semiconductor device comprising:
- a plurality of cores each including an instruction execution circuit that executes an instruction and a first cache that holds at least one of an instruction and data used in the instruction execution circuit;
- a second cache shared by the plurality of cores;
- and
- a cache control circuit that controls switching of a cache line size used in the first cache and the second cache,
- wherein each of the plurality of cores further including
- an instruction collection circuit that collects, at time intervals during a collection period, a number of completed instructions for each type of the instructions that are executed by the instruction execution circuit, and calculates an execution frequency for each type of the instructions at an end of the collection period, and
- a first selection circuit that selects a cache line size for use in the first cache based on the execution frequency calculated by the instruction collection circuit during the collection period, and
- the cache control circuit determines a cache line size used in the first cache and the second cache based on cache line sizes selected by the first selection circuit of the plurality of cores.
A cache control method for switching a cache line size in a semiconductor device comprising:
- a plurality of cores each including an instruction execution circuit that executes an instruction and a first cache that holds at least one of an instruction and data used in the instruction execution circuit;
- and
- a second cache shared by the plurality of cores;
- the method including:
- collecting, for each of the plurality of cores, at time intervals during a collection period, a number of completed instructions for each type of the instructions that are executed by the instruction execution circuit;
- calculating, for each of the plurality of cores, an execution frequency for each type of the instructions at an end of the collection period,
- selecting, for each of the plurality of cores, a cache line size for use in the first cache based on the execution frequency calculated, and
- determining a cache line size used in the first cache and the second cache based on cache line sizes selected for the plurality of cores.
Dependencies are inferred from the claim text.