US 2022/0027271 A1Published application

Cache operations in a hybrid dual in-line memory module

AssigneeMicron Technology, Inc.

InventorsPaul Stonelake, Horia C. Simionescu, Samir Mittal, Robert W. Walker, Anirban Ray, Gurpreet Anand

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Abstract

A system includes a first memory device of a first memory type, a second memory device of a second memory type, and a third memory device of a third memory type. The system further includes a processing device to retrieve one or more sections of data from the first memory device comprising a first memory type, and retrieve one or more remaining sections of data from the second memory device comprising a second memory type, wherein the one or more remaining sections of data from the second memory device are associated with the one or more sections of data from the first memory device. The processing device is further to combine the one or more sections of data from the first memory device comprising the first memory type with the one or more remaining sections of each of data from the second memory device comprising the second memory type into a contiguous page, and copy the contiguous page to a third memory device comprising a third memory type.

Claims20

Dependent claims

A system comprising:

a first memory device comprising a first memory type;
a second memory device comprising a second memory type coupled to the first memory device;
a third memory device comprising a third memory type coupled to the first memory device and the second memory device, wherein the third memory type has a higher access latency than the first memory device, and wherein the second memory device has a higher access latency than the first and third memory devices;
and
a processing device, operatively coupled with the first memory device, the second memory device, and the third memory device, to perform operations comprising:
retrieving one or more sections of data from the first memory device comprising the first memory type;
retrieving one or more remaining sections of data from the second memory device comprising the second memory type, wherein the one or more remaining sections of data from the second memory device are associated with the one or more sections of data from the first memory device;
combining the one or more sections of data from the first memory device comprising the first memory type with the one or more remaining sections of each of data from the second memory device comprising the second memory type into a contiguous page;
and
copying the contiguous page to the third memory device comprising the third memory type.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/450,124Filed 6 Oct 2021
Priority: 17 Sep 2018
Published: 27 Jan 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 12/0811
Multiuser, multiprocessor or multiprocessing cache systems: with multilevel cache hierarchies
G06F 12/0862
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with prefetch
G06F 12/0888
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…
G06F 12/0897
Caches characterised by their organisation or structure: with two or more cache hierarchy levels

Family

Application62/732,191Us provisional application · filed 17 Sep 2018
Application16/573,305Continuation · filed 17 Sep 2019
Application17/450,124Continuation
US 11,169,920 B2Related patent
US 11,561,902 B2Related patent
US 2020/0089610 A1Published application
US 2022/0027271 A1This patent

From the US filing history. Foreign family members aren’t listed.