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US 2022/0027236 A1Published application
Memory devices and methods for managing error regions
AssigneeMicron Technology, Inc.
InventorJoe M. Jeddeloh
Life of this patent
Estimating the term…
Abstract
Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.
Claims20
A memory device, comprising:
- a stack of multiple memory die electrically connected with one another by through wafer interconnects extending through the stack of multiple memory die, the stack of multiple memory die comprising multiple partitions, each partition including one or more arrays from each of two or more memory die of the stack of multiple memory die;
- and
- control logic operably coupled to the stack of multiple memory die, the control logic operable to monitor portions of the stack of multiple memory die to collect error data indicating defective portions within one or more of the partitions, and to remove a defective portion from one or more of the multiple partitions;
- and
- wherein the stack of multiple memory die comprises multiple first partitions established according to a first memory map, each partition including one or more arrays from each of two or more memory die of the stack of multiple memory die.
2 more elements
A memory device, comprising:
- a logic die containing control logic circuitry;
- a stack of DRAM memory die, wherein each DRAM die of the stack of DRAM memory die is interconnected with at least one other DRAM die of the stack of DRAM memory die by through multiple wafer interconnects;
- and
- the stack of DRAM memory die allocated according to a first partition state establishing multiple first partitions, each partition including one or more arrays from each of two or more DRAM die of the stack of DRAM memory die;
- and
- wherein the control logic circuitry is operable to monitor portions of the stack of DRAM memory die to collect error data indicating a defective portion within one or more of the partitions, and to remove the defective portion from one or more of the multiple first partitions.
3 more elements
Dependencies are inferred from the claim text.