Validating machine-readable instructions using an iterative validation process

A non-transitory machine-readable storage medium comprising instructions that upon execution cause a first processor to:

• perform an iterative validation process comprising a plurality of iterations performed at different times for validating a program executable on a second processor different from the first processor, wherein the iterative validation process comprises:
• in a first iteration:
• issue a first challenge to the second processor to compute a first value based on a first subset of the program, wherein the first challenge includes first subset information identifying a first subset of stored information including the program,
• receive, from the second processor, the first value in response to the first challenge, and
• determine whether the program is valid based on the first value received from the second processor;
• and
• in a second iteration:
• issue a second challenge to the second processor to compute a second value based on a second subset of the program, wherein the second challenge includes second subset information identifying a second subset of the stored information,
• receive, from the second processor, the second value in response to the first challenge, and
• determine whether the program is valid based on the second value received from the second processor.

A method of a system comprising a first processor and a second processor, comprising;

• performing, by the first processor, an iterative validation process to validate machine-readable instructions executable on the second processor, the iterative validation process comprising a plurality of iterations performed at different times, each respective iteration of the plurality of iterations comprising:
• issuing, from the first processor, a respective indication to the second processor to compute a value based on a respective randomly selected subset of stored information comprising the machine-readable instructions, wherein the respective indication includes a respective memory address range that identifies the respective randomly selected subset as selected by the first processor, and wherein the respective memory address range differs from a different memory address range included in another indication issued from the first processor to the second processor in another iteration of the plurality of iterations, the different memory address range identifying a different randomly selected subset of the stored information as selected by the first processor, and
• determining a validity of the machine-readable instructions based on the value returned to the first processor by the second processor,
• wherein different iterations of the iterative validation process can produce different validation results relating to validating the machine-readable instructions.