Distribution of Logical-to-Physical Address Entries Across Multiple Memory Areas
AssigneeWestern Digital Technologies, Inc.
InventorsJameer MULANI, Kapil SUNDRANI, Anindya RAI
Life of this patent
Estimating the term…
Abstract
A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.
Claims20
A method for a storage system, comprising:
- writing logical-to-physical address entries of an address data structure into one or more memories comprising a first memory area and a second memory area, wherein the second memory area is different from the first memory area;
- performing first multiple access requests, wherein the first multiple access requests are directed to one of the first and second memory areas but not both of the first and second memory areas;
- and
- performing second multiple access requests, wherein a first one of the second multiple access requests is directed to a first one of the first and second memory areas, wherein a second one of the second multiple access requests is directed to a second one of the first and second memory areas, and wherein the second one is different from the first one,
- wherein the second multiple access requests are performed faster than the first multiple access requests.
A storage system, comprising:
- one or more memories comprising a first memory area and a second memory area, wherein the second memory area is different from the first memory area;
- and
- one or more controllers configured to cause:
- writing logical-to-physical address entries of an address data structure into the one or more memories;
- performing first multiple access requests, wherein the first multiple access requests are directed to one of the first and second memory areas but not both of the first and second memory areas;
- and
- performing second multiple access requests, wherein a first one of the second multiple access requests is directed to a first one of the first and second memory areas, wherein a second one of the second multiple access requests is directed to a second one of the first and second memory areas, and wherein the second one is different from the first one,
- wherein the one or more controllers are configured to cause performing the second multiple access requests faster than performing the first multiple access requests.
An apparatus, comprising:
- means for writing logical-to-physical address entries of an address data structure into one or more memories comprising a first memory area and a second memory area, wherein the second memory area is different from the first memory area;
- means for performing first multiple access requests, wherein the first multiple access requests are directed to one of the first and second memory areas but not both of the first and second memory areas;
- and
- means for performing second multiple access requests, wherein a first one of the second multiple access requests is directed to a first one of the first and second memory areas, wherein a second one of the second multiple access requests is directed to a second one of the first and second memory areas, and wherein the second one is different from the first one,
- wherein the apparatus is configured to cause performing the second multiple access requests faster than performing the first multiple access requests.
Dependencies are inferred from the claim text.