Relocating data to low latency memory

A system comprising:

• a memory device;
• and
• a processing device coupled with the memory device, to perform operations comprising:
• identifying a plurality of word lines at a first portion of the memory device;
• determining a respective error rate for each of the plurality of word lines;
• determining that a first error rate of a first word line of the plurality of word lines and a second error rate of a second word line of the plurality of word lines satisfy a first threshold condition pertaining to an error rate threshold;
• identifying a third word line of the plurality of word lines that is proximate to the first word line and the second word line;
• and
• relocating data stored at the third word line to a second portion of the memory device, wherein the second portion of the memory device is associated with a lower read latency than the first portion of the memory device.

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

• identifying a plurality of word lines at a first portion of a memory device;
• determining a respective error rate for each of the plurality of word lines;
• determining that a first error rate of a first word line of the plurality of word lines and a second error rate of a second word line of the plurality of word lines satisfy a first threshold condition pertaining to an error rate threshold;
• identifying a third word line of the plurality of word lines that is proximate to the first word line and the second word line;
• and
• relocating data stored at the third word line to a second portion of the memory device, wherein the second portion of the memory device is associated with a lower read latency than the first portion of the memory device.