Failure pattern obtaining method and apparatus

A failure pattern obtaining apparatus, comprising:

• a processor;
• and
• a memory configured to store instructions executed by the processor,
• wherein the processor is configured to:
• obtain a chip test result picture for a wafer, the chip test result picture being marked with a plurality of failure test points;
• calculate a vector for every two points among all of the failure test points;
• designate a plurality of failure test points having a same vector as a same group and obtain a plurality of groups;
• separate a plurality of pending failure patterns from each of groups;
• and
• obtain a failure pattern based on the plurality of the pending failure patterns.

A system for monitoring test equipment, comprising:

• a failure pattern obtaining apparatus, configured to obtain a failure pattern by the following operations:
• obtaining a chip test result picture for a wafer, the chip test result picture being marked with a plurality of failure test points;
• calculating a vector for every two points among all of the failure test points;
• designating a plurality of failure test points having a same vector as a same group and obtaining a plurality of groups;
• separating a plurality of pending failure patterns from each of the groups;
• and
• obtaining the failure pattern based on the plurality of the pending failure patterns;
• and
• test equipment, configured to determine whether a failure pattern exists on the chip test result picture, and check a test environment of the test equipment responsive to determining that the failure pattern exists on the chip test result picture.