3-dimensional nor string arrays in segmented stacks
AssigneeSunrise Memory Corporation
InventorsEli Harari, Wu-Yi Chien
Life of this patent
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Abstract
A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.
Claims8
A process for forming a memory structure, comprising:
- providing a semiconductor substrate having a planar surface;
- forming a first memory module above the planar surface, such that the first memory module includes a 3-dimensional array of NOR-type memory strings that comprises a plurality of NOR-type memory strings, with (i) two or more of the NOR-type memory strings being separated from each other along a first direction that is substantially parallel the planar surface and two or more of the NOR-type memory strings being separated from each other along a second direction that is orthogonal to the first direction and substantially perpendicular the planar surface, (ii) each of the NOR-type memory strings comprising a plurality of thin-film storage transistors, and (iii) a set of local word line conductors, each running along the second direction to serve as gate electrodes to the thin-film storage transistors of one or more of the NOR-type memory strings;
- forming a first set of global conductors, such that the global conductors are (i) spaced from each other along a third direction that is substantially orthogonal both the first and second directions and (ii) each running along the first direction, in direct contact with selected local word line conductors of the first memory module;
- forming a second memory module above the first memory module and the first set of global conductors, such that the second memory module also includes a 3-dimensional array of NOR-type memory strings that comprises a plurality of NOR-type memory strings, with (i) two or more of the NOR-type memory strings being separated from each other along the first direction and two or more of the NOR-type memory strings being separated from each other along the second direction, (ii) each of the NOR-type memory strings comprising a plurality of thin-film storage transistors, and (iii) a set of local word line conductors, each running along the second direction to serve as gate electrodes to the thin-film storage transistors of one or more of the NOR-type memory strings, and such that the first set of global conductors are also each in direct contact with selected local word line conductors of the second memory module.
Dependencies are inferred from the claim text.