Packet switch and packet period determination method
AssigneeFujitsu Limited
InventorYoshikazu Sabetto
Life of this patent
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Abstract
A packet switch that determines a time slot for closing transmission of low-priority packets based on a determination result of periods of high-priority packets having periodicity, the packet switch includes: a memory; and a processor coupled to the memory and configured to: determine, for respective input ports, the periods of the input high-priority packets; and determine a setting period of a gate control list in which the time slot for closing is set, based on the determined periods of the high-priority packets.
Claims11
A packet switch that determines a time slot for closing transmission of low-priority packets based on a determination result of periods of high-priority packets having periodicity, the packet switch comprising:
- a memory;
- and
- a processor coupled to the memory and configured to:
- determine, for respective input ports, the periods of the input high-priority packets;
- and
- determine a setting period of a gate control list in which the time slot for closing is set, based on the determined periods of the high-priority packets.
A packet period determination method for determining a time slot for closing transmission of low-priority packets, based on a determination result of periods of high-priority packets having periodicity, the method comprising:
- a period determination process of determining each of the periods of the input high-priority packets for respective input ports;
- and
- a closing TS determination process of determining a setting period of a gate control list in which the time slot for closing is set, based on the periods of the plurality of high-priority packets each determined in the period determination process.
Dependencies are inferred from the claim text.