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US 2022/0021384 A1Published application
Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals
AssigneepSemi Corporation
InventorsTero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
Life of this patent
Estimating the term…
Abstract
Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
Claims23
(canceled)
An integrated circuit block comprising:
- a first node;
- a second node;
- and
- a series arrangement of three or more field-effect transistors (FET);
- wherein:
- i) the three or more FETs are configured to:
- a) be connected in series with a series arrangement of one or more capacitors to couple a combination of the one or more capacitors and the three or more FETs between the first node and the second node;
- b) withstand a voltage greater than a voltage withstood by one FET of the three or more FETs;
- and
- c) receive a control signal to enable or disable the FETs thereby adjusting the capacitance between the first node and the second node, and
- ii) one or more compensation capacitors are coupled to a drain terminal of at least one of the three or more FETs.
8 more elements
An integrated circuit block comprising:
- a first node;
- a second node;
- and
- a series arrangement of two or more field-effect transistors (FET),
- wherein:
- i) the two or more FETs are configured to:
- a) be connected in series with a series arrangement of one or more capacitors to couple a combination of the one or more capacitors and the two or more FETs between the first node and the second node;
- and
- b) withstand a voltage greater than a voltage withstood by one FET of the two or more FETs;
- ii) each of the two or more FETs has a control node configured to receive a control signal to enable or disable the two or more FETs, and thereby adjusting the capacitance between the first node and the second node;
- and
- iii) compensation capacitors are coupled to a drain terminal of at least one of the two or more FETs.
9 more elements
An integrated circuit block comprising:
- a first node;
- a second node;
- a series arrangement of one or more capacitors;
- a series arrangement of a plurality of field-effect transistors (FET), and
- a first compensation capacitor;
- and
- wherein:
- the one or more capacitors are in series with the plurality of FETs;
- a combination of the one or more capacitors and the plurality of FETs is coupled between the first node and the second node;
- the plurality of FETs are configured to withstand a voltage greater than a voltage withstood by one FET;
- the plurality of FETs are configured to receive a control signal to enable or disable the FETs, thereby adjusting the capacitance between the two nodes, and
- the first compensation capacitor is connected to a drain terminal of one or more FETs of the plurality of FETs.
9 more elements
Dependencies are inferred from the claim text.