Semiconductor device having upper channel and lower channel and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorSungmin KIM
Life of this patent
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Abstract
A semiconductor device and a method of manufacturing a semiconductor device, the device including a first semiconductor pattern on a substrate, the first semiconductor pattern including a lower channel; a second semiconductor pattern on the first semiconductor pattern and spaced apart from the first semiconductor pattern in a vertical direction, the second semiconductor pattern including an upper channel extending in the vertical direction; a gate electrode covering the lower channel and surrounding the upper channel; and source/drain patterns on opposite sides of the upper channel, wherein the substrate and the first semiconductor pattern have a doping concentration of 1019/cm3 or less.
Claims20
A semiconductor device, comprising:
- a first semiconductor pattern on a substrate, the first semiconductor pattern including a lower channel;
- a second semiconductor pattern on the first semiconductor pattern and spaced apart from the first semiconductor pattern in a vertical direction, the second semiconductor pattern including an upper channel extending in the vertical direction;
- a gate electrode covering the lower channel and surrounding the upper channel;
- and
- source/drain patterns on opposite sides of the upper channel,
- wherein the substrate and the first semiconductor pattern have a doping concentration of 1019/cm3 or less.
A semiconductor device, comprising:
- a first semiconductor pattern on a substrate, the first semiconductor pattern including an extension pattern protruding from an upper surface of the substrate and a lower channel on the extension pattern;
- a semiconductor oxide layer between the extension pattern and the lower channel;
- a device isolation layer covering the substrate and the semiconductor oxide layer;
- a second semiconductor pattern on the first semiconductor pattern and spaced apart from the first semiconductor pattern in a vertical direction, the second semiconductor pattern including an upper channel extending in the vertical direction;
- a gate electrode covering the lower channel and surrounding the upper channel;
- a gate capping layer covering the gate electrode;
- and
- source/drain patterns on opposite sides of the upper channel,
- wherein the substrate and the first semiconductor pattern have a doping concentration of 1019/cm3 or less.
A method of manufacturing a semiconductor device, the method comprising:
- forming an active pattern including a first semiconductor pattern on a substrate, a sacrificial pattern on the first semiconductor pattern, and a second semiconductor pattern on the sacrificial pattern, the active pattern extending in a first horizontal direction;
- forming a preliminary gate pattern extending in a second horizontal direction, intersecting the first horizontal direction, across the active pattern;
- forming a cavity by removing a portion of the sacrificial pattern that does not overlap the preliminary gate pattern in a vertical direction;
- forming an insulating pattern filling the cavity and gate spacers covering a sidewall of the preliminary gate pattern;
- forming source/drain patterns on the second semiconductor pattern;
- and
- replacing the preliminary gate pattern with a gate electrode,
- wherein the substrate and the first semiconductor pattern have a doping concentration of 1019/cm3 or less.
Dependencies are inferred from the claim text.