# US 2022/0020847 A1 · Semiconductor structure and manufacturing method thereof

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- Number: US 2022/0020847 A1
- Document ID: US20220020847A1
- Status: Published application
- Kind: A1
- Application number: 16/930,328
- Filed: 2020-07-16
- Published: 2022-01-20
- Earliest claimed: 2020-07-16
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Ting-Cih KANG; Hsih-Yang CHIU
- Web page: https://patentgrep.com/patent/US20220020847A1

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10W 90/00: Package configurations
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P 90/12: {Preparing bulk and homogeneous wafers}
- H10W 72/00: Interconnections or connectors in packages
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/071: {Connecting or disconnecting}
- H10W 72/90: Bond pads, in general
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/931: {Shapes of bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/792: {between multiple chips}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.

## Claims

### Claim at position 1

1-13. (canceled)

### Claim 14

A semiconductor structure, comprising:
a lower dielectric layer;
at least one lower metallization structure embedded in the lower dielectric layer;
an upper dielectric layer forming a dielectric-to-dielectric bond with the lower dielectric layer; and
at least one upper metallization structure embedded in the upper dielectric layer and forming a metal-to-metal bond with the lower top metallization structure, and the dielectric-to-dielectric bond and the metal-to-metal bond are located at different levels.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein the metal-to-metal bond is laterally surrounded by the upper dielectric layer.

### Claim 16 (depends on 14)

The semiconductor structure of claim 14, wherein the lower metallization structure and the upper metallization structure comprise a same material.

### Claim 17 (depends on 14)

The semiconductor structure of claim 14, further comprising an etch stop layer laterally extending over the upper dielectric layer and the upper metallization structure.

### Claim 18 (depends on 14)

The semiconductor structure of claim 14, further comprising at least one conductive plug vertically through the etch stop layer and in contact with the upper metallization structure.

### Claim 19 (depends on 18)

The semiconductor structure of claim 18, further comprising at least one top metallization structure, and the conductive plug is vertically between the top metallization structure and the upper metallization structure.

### Claim 20 (depends on 14)

The semiconductor structure of claim 14, further comprising at least one bottom metallization structure and at least one conductive plug vertically between the lower metallization structure and the bottom metallization structure.