US 2022/0020814 A1Published application

Hall integrated circuit and corresponding method of manufacturing of a hall integrated circuit using wafer stacking

AssigneeLfoundry S.R.L.

InventorsCarsten SCHMIDT, Mario BLASINI, Gerhard SPITZLSPERGER, Alessandro MONTAGNA

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Abstract

A Hall integrated circuit including a vertical Hall element, having a first wafer and a second wafer, the second wafer including a CMOS substrate integrating a CMOS processing circuit coupled to the vertical Hall element and a stack of dielectric layers, and the first wafer including a Hall-sensor layer having a first surface and a second surface, the first and second wafers being bonded with the interposition of a dielectric layer arranged above the first surface of the Hall-sensor layer. The vertical Hall element has: at least a first Hall terminal; at least a second Hall terminal; a deep trench isolation ring extending through the Hall-sensor layer from the first surface to the second surface and enclosing and isolating a Hall sensor region of the Hall-sensor layer; and a first and a second conductive structures electrically connected to respective contact pads embedded in the stack of the second wafer.

Claims15

Dependent claims

A Hall integrated circuit including a vertical Hall element, comprising a first wafer and a second wafer stacked in a vertical direction, the second wafer comprising a CMOS substrate integrating a CMOS processing circuit configured to be coupled to the vertical Hall element and a stack of dielectric layers arranged on the CMOS substrate, and the first wafer comprising a Hall-sensor layer having a first surface and a second surface opposed along the vertical direction and extending in a horizontal plane, orthogonal to the vertical direction, the first and second wafers being bonded with the interposition of a dielectric layer arranged above the first surface of the Hall-sensor layer,

wherein the vertical Hall element 100 comprises:
at least a first Hall terminal, being a first doped region arranged at the first surface of the Hall-sensor layer;
at least a second Hall terminal, being a second doped region arranged at the second surface of the Hall-sensor layer aligned to the first doped region along the vertical direction and separated therefrom by the thickness of the Hall-sensor layer;
a deep trench isolation ring extending through the Hall-sensor layer from the first surface to the second surface and enclosing and isolating a Hall sensor region of the Hall-sensor layer, wherein the first and second Hall terminals are arranged;
and
a first and a second conductive structure coupled to the first, respectively, the second Hall terminal and configured to be electrically connected to respective contact pads embedded in the stack of the second wafer.

3 more elements

A method of manufacturing of a Hall integrated circuit including a vertical Hall element, comprising forming a stack in a vertical direction of:

a first wafer including a Hall-sensor layer having a first surface and a second surface opposed along the vertical direction and extending in a horizontal plane, orthogonal to the vertical direction;
and
a second wafer including a CMOS substrate integrating a CMOS processing circuit configured to be coupled to the vertical Hall element and a stack of dielectric layers arranged on the CMOS substrate,
wherein the first and second wafers are bonded with the interposition of a dielectric layer arranged above the first surface of the Hall-sensor layer, and
wherein the vertical Hall element comprises:
at least a first Hall terminal, being a first doped region arranged at the first surface of the Hall-sensor layer;
at least a second Hall terminal, being a second doped region arranged at the second surface of the Hall-sensor layer aligned to the first doped region along the vertical direction and separated therefrom by the thickness of the Hall-sensor layer;
a deep trench isolation ring extending through the Hall-sensor layer from the first surface to the second surface and enclosing and isolating a Hall sensor region of the Hall-sensor layer, wherein the first and second Hall terminals are arranged;
and
a first and a second conductive structures coupled to the first, respectively, the second Hall terminal and configured to be electrically connected to respective contact pads embedded in the stack of the second wafer.

7 more elements

Dependencies are inferred from the claim text.