Memory cell arrangement and methods thereof

An arrangement of capacitor-based memory cells, the arrangement comprising:

• a first electrode layer comprising at least a first through hole, a second through hole, a third through hole, and a fourth through hole, each of the first through hole, the second through hole, the third through hole, and the fourth through hole extending from a first surface of the first electrode layer to a second surface of the first electrode layer, wherein the second surface is opposite the first surface;
• a second electrode layer comprising at least a first through hole, a second through hole, a third through hole, and a fourth through hole, each of the first through hole, the second through hole, the third through hole, and the fourth through hole extending from a first surface of the second electrode layer to a second surface of the second electrode layer, wherein the second surface is opposite the first surface;
• a first electrode pillar, wherein a first portion of the first electrode pillar is disposed within the first through hole of the first electrode layer and wherein a second portion of the first electrode pillar is disposed within the first through hole of the second electrode layer;
• a second electrode pillar, wherein a first portion of the second electrode pillar is disposed within the second through hole of the first electrode layer and wherein a second portion of the second electrode pillar is disposed within the second through hole of the second electrode layer;
• a third electrode pillar, wherein a first portion of the third electrode pillar is disposed within the third through hole of the first electrode layer and wherein a second portion of the third electrode pillar is disposed within the third through hole of the second electrode layer;
• a fourth electrode pillar, wherein a first portion of the fourth electrode pillar is disposed within the fourth through hole of the first electrode layer and wherein a second portion of the fourth electrode pillar is disposed within the fourth through hole of the second electrode layer;
• a first memory material portion disposed at least within the first through hole of the first electrode layer in a gap between the first electrode layer and the first portion of the first electrode pillar that is disposed within the first through hole of the first electrode layer;
• a second memory material portion disposed at least within the first through hole of the second electrode layer in a gap between the second electrode layer and the second portion of the first electrode pillar that is disposed within the first through hole of the second electrode layer;
• a third memory material portion disposed at least within the second through hole of the first electrode layer in a gap between the first electrode layer and the first portion of the second electrode pillar that is disposed within the second through hole of the first electrode layer;
• and
• a fourth memory material portion disposed at least within the second through hole of the second electrode layer in a gap between the second electrode layer and the second portion of the second electrode pillar that is disposed within the second through hole of the second electrode layer;
• a fifth memory material portion disposed at least within the third through hole of the first electrode layer in a gap between the first electrode layer and the first portion of the third electrode pillar that is disposed within the third through hole of the first electrode layer;
• a sixth memory material portion disposed at least within the third through hole of the second electrode layer in a gap between the second electrode layer and the second portion of the third electrode pillar that is disposed within the third through hole of the second electrode layer;
• a seventh memory material portion disposed at least within the fourth through hole of the first electrode layer in a gap between the first electrode layer and the first portion of the fourth electrode pillar that is disposed within the fourth through hole of the first electrode layer;
• an eighth memory material portion disposed at least within the fourth through hole of the second electrode layer in a gap between the second electrode layer and the second portion of the fourth electrode pillar that is disposed within the fourth through hole of the second electrode layer;
• wherein the first electrode layer, the first portion of the first electrode pillar, and the first memory material portion form a first memory cell;
• wherein the second electrode layer, the second portion of the first electrode pillar, and the second memory material portion form a second memory cell;
• wherein the first electrode layer, the first portion of the second electrode pillar, and the third memory material portion form a third memory cell;
• wherein the second electrode layer, the second portion of the second electrode pillar, and the fourth memory material portion form a fourth memory cell;
• wherein the first electrode layer, the first portion of the third electrode pillar, and the fifth memory material portion form a fifth memory cell;
• wherein the second electrode layer, the second portion of the third electrode pillar, and the sixth memory material portion form a sixth memory cell;
• wherein the first electrode layer, the first portion of the fourth electrode pillar, and the seventh memory material portion form a seventh memory cell;
• wherein the second electrode layer, the second portion of the fourth electrode pillar, and the eighth memory material portion form an eighth memory cell;
• a first access device configured to connect a first bitline to the first electrode pillar controlled by a voltage applied at a first wordline;
• a second access device configured to connect the first bitline to the second electrode pillar controlled by a voltage applied at a second wordline;
• a third access device configured to connect a second bitline to the third electrode pillar controlled by a voltage applied at the first wordline;
• a fourth access device configured to connect the second bitline to the fourth electrode pillar controlled by a voltage applied at the second wordline;
• a control circuit configured to address one of the first memory cell, the second memory cell, the third memory cell, the fourth memory cell, the fifth memory cell, the sixth memory cell, the seventh memory cell, or the eighth memory cell by supplying a first voltage to the associated one of the first bitline or the second bitline, a second voltage to the associated one of the first wordline or the second wordline, and a third voltage to the associated one of the first electrode layer or the second electrode layer.

Method of operating a memory cell arrangement, the method comprising:

• supplying a voltage to an electrode pillar associated with a memory cell to be addressed selected from a plurality of memory cells via an access device corresponding to the electrode pillar by supplying a first voltage to a first control line associated with the memory cell to be addressed and by supplying a second voltage to a second control line associated with the memory cell to be addressed, wherein other memory cells of the plurality of memory cells are not addressed;
• supplying a voltage to an electrode layer associated with the memory cell to be addressed by supplying a third voltage to a third control line corresponding to the electrode layer;
• supplying a first inhibit voltage to one or more first control lines of a plurality of first control lines not corresponding to the memory cell to be addressed;
• supplying a second inhibit voltage to one or more second control lines of a plurality of second control lines not corresponding to the memory cell to be addressed;
• and
• supplying a third inhibit voltage to one or more third control lines of a plurality of third control lines not corresponding to the memory cell to be addressed, wherein the third inhibit voltage is configured to prohibit that one or more memory cells not to be addressed change into another one of at least two memory states of the respective memory cell.