Semiconductor memory device and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsByung Chul JANG, Sang-Yong PARK, Jae Duk LEE
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a stacked structure on a substrate and a vertical structure penetrating the stacked structure. The stacked structured includes a plurality of conductive lines stacked on the substrate. The vertical structure may include a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern. The vertical insulating pattern may include an inner region and an outer region. The outer region of the vertical insulating pattern may be placed between the channel film and the inner region of the vertical insulating pattern, and the outer region of the vertical insulating pattern may include a diffused metal.
Claims20
A semiconductor memory device comprising:
- a substrate;
- a stacked structure on the substrate, the stacked structure including a plurality of conductive lines stacked on the substrate;
- and
- a vertical structure penetrating the stacked structure, the vertical structure including a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern,
- the vertical insulating pattern including an inner region and an outer region,
- the outer region of the vertical insulating pattern being between the channel film and the inner region of the vertical insulating pattern, and
- the outer region of the vertical insulating pattern including a diffused metal.
A semiconductor memory device comprising:
- a substrate;
- a stacked structure on the substrate, the stacked structure including a plurality of conductive lines stacked on the substrate;
- and
- a vertical structure penetrating the stacked structure, the vertical structure including a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern,
- the vertical insulating pattern includes a diffused metal, and
- the channel film includes a metal silicide including the diffused metal.
A semiconductor memory device comprising:
- a substrate;
- a peripheral logic structure on the substrate and including a peripheral circuit;
- a horizontal conductive substrate extending along an upper surface of the peripheral logic structure;
- a stacked structure on the horizontal conductive substrate, the stacked structure including a plurality of conductive lines stacked on the horizontal conductive substrate;
- and
- a vertical structure penetrating the stacked structure, the vertical structure including a memory cell insulating film, a vertical insulating pattern, and a channel film between the memory cell insulating film and the vertical insulating pattern,
- the vertical insulating pattern including an inner region and an outer region,
- the outer region of the vertical insulating pattern being between the channel film and the inner region of the vertical insulating pattern,
- the outer region of the vertical insulating pattern including a diffused metal, and
- the channel film including the diffused metal.
Dependencies are inferred from the claim text.