Dual port memory cell with improved access resistance
AssigneeSTMicroelectronics International N.V.
InventorsTushar SHARMA, Tanmoy ROY, Shishir KUMAR
Life of this patent
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Abstract
The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.
Claims20
A method, comprising:
- forming a dual port bit memory cell, the forming including:
- forming a first active region in a semiconductor layer, the first active region having a first width in a first direction and a first length in a second direction orthogonal to the first direction, the first length more than three times the first width, the forming the first active region including:
- forming a first bit line node;
- forming a first memory cell node;
- forming a first power line node in the first active region, the first power line node having a width equal to the first width;
- forming a second memory cell node;
- and
- forming a first inverted bit line node;
- and
- forming a plurality of gates on the semiconductor layer, the forming the plurality of gates including:
- forming a first gate that selectively couples the first bit line node to the first memory cell node;
- forming a second gate that selectively couples the first memory cell node to the first power line node;
- forming a third gate that selectively couples the first power line node to the second memory cell node;
- and
- forming a fourth gate that selectively couples the second memory cell node to the first inverted bit line node.
A method, comprising:
- forming in a semiconductor substrate, a first active area and a second active area spaced away from one another,
- the first active area including:
- a first bit line node,
- a first memory cell node,
- a first power line node,
- a second memory cell node, and
- a first inverted bit line node, and
- the second active area including:
- a second bit line node,
- a third memory cell node,
- a second power line node,
- a fourth memory cell node, and
- a second inverted bit line node;
- and
- forming a first metallization level over the semiconductor substrate, the first metallization level including:
- a first routing line coupling the first memory cell node to the third memory cell node, and
- a second routing line coupling the second memory cell node to the fourth memory cell node.
A method, comprising:
- forming in each of a first active region and a second active region in a semiconductor layer by:
- forming a first transistor between a first bit line node and a first memory cell node;
- forming a second transistor between the first memory cell node and a first power line node;
- forming a third transistor between the first power line node and a second memory cell node;
- and
- forming a fourth transistor between the second memory cell node and a first inverted bit line node, a gate of the second transistor in the first active region coupled to a gate of the second transistor in the second active region, and a gate of the third transistor in the first active region coupled to a gate of the third transistor in the second active region.
Dependencies are inferred from the claim text.