High performance nanosheet fabrication method with enhanced high mobility channel elements

A semiconductor device, comprising:

• a plurality of transistor pairs formed over a substrate, arranged side by side, and coupled to one another, each of the plurality of transistor pairs including a n-type transistor and a p-type transistor that are stacked over one another, wherein
• the n-type transistor has a first channel region that includes one or more first nano-channels made of a first compound material having a first bandgap value based on a first predetermined material ratio in the first compound material, the one or more first nano-channels extending laterally along the substrate, being stacked over the substrate and spaced apart from one another;
• the p-type transistor has a second channel region that includes one or more second nano-channels made of a second compound material having a second bandgap value based on a second predetermined material ratio in the second compound material, the one or more second nano-channels extending laterally along the substrate, being stacked over the substrate and spaced apart from one another;
• each of the one or more first nano-channels in the first channel region of the n-type transistor and each of the one or more second nano-channels in the second channel region of the p-type transistor are surrounded by a gate structure respectively;
• the n-type transistor includes a first source/drain (S/D) region and a second S/D region, the first S/D region and the second S/D region of the n-type transistor being positioned at two ends of the one or more first nano-channels and in direct contact with the one or more first nano-channels, at least one of the first S/D region and the second S/D region of the n-type transistor being coupled to a first channel region of an adjacent n-type transistor;
• and
• the p-type transistor further comprises a first source/drain (S/D) region and a second S/D region, the first S/D region and the second S/D region of the p-type transistor being positioned at two ends of the one or more second nano-channels and in direct contact with the one or more second nano-channels, at least one of the first S/D region and the second S/D region of the p-type transistor being coupled to a second channel region of an adjacent p-type transistor.