Three-dimensional (3d) integrated circuit device having a backside power delivery network

A method for fabricating a 3D IC device integration package, comprising:

• concurrently forming a power delivery network on a temporary carrier wafer and forming a material separation layer within a semiconductor substrate;
• bonding an exposed surface of the power delivery network to an active layer of the semiconductor substrate;
• separating the semiconductor substrate at the material separation layer to expose a surface of the active layer;
• forming a first die from the active layer having a first surface opposite the active layer;
• and
• bonding a second die to the first surface of the first die.

An integrated circuit (IC) package, comprising:

• a power delivery network;
• a first die having a first surface and a second surface, opposite the first surface, the second surface on a first surface of the power delivery network;
• means for storing data having a first surface on the first surface of the first die;
• and
• package bumps on a second surface of the power delivery network, opposite the first surface of the power delivery network, and coupled to contact pads of the power delivery network.