Semiconductor package

A semiconductor package, comprising:

• a package substrate comprising a first package surface in which an insulating layer is disposed, the insulating layer comprising openings;
• at least one first semiconductor chip comprising a first surface in contact with the first package surface and a second surface opposing the first surface and comprising bonding pads disposed proximate to one edge thereof, the first surface comprising first and second corners disposed at both ends of the one edge and third and fourth corners disposed on opposite ends of the other edge;
• and
• at least one second semiconductor chip stacked on the second surface in the form of a staircase,
• wherein the insulating layer comprises a first region comprising the openings and a second region, wherein the second region is a remaining region of insulating layer disposed on the base substrate, other than the first region, and
• wherein the first and second corners overlap the second region, and the third and fourth corners overlap the first region.

A semiconductor package, comprising:

• a package substrate comprising one surface in which an insulating layer is disposed, the insulating layer comprising first and second openings;
• and
• at least one semiconductor chip stack comprising a plurality of semiconductor chips stacked on the one surface of the package substrate in the form of a staircase,
• wherein a plurality of the semiconductor chips comprises:
• a first semiconductor chip comprising a tetragonal mounting region defined by first and second edges opposing each other and third and fourth edges connecting the first and second edges and a plurality of bonding pads disposed closely to the first edge;
• and
• at least one second semiconductor chip stacked on the first semiconductor chip in the form of a staircase,
• wherein both ends of the second edges overlap the first and second openings.