Semiconductor package device

A semiconductor package device, comprising:

• a redistribution substrate,
• the redistribution substrate including an insulating layer, an under-bump pattern and an outer coupling terminal, the under-bump pattern in the insulating layer and partially exposed to an outside of the insulating layer, and the outer coupling terminal on the under-bump pattern, the under-bump pattern including a body portion and a protruding portion extending from the body portion,
• the protruding portion having a top surface and a side surface, the top surface of the protruding portion being spaced apart from the body portion, and the side surface of the protruding portion connecting the top surface of the protruding portion to a top surface of the body portion, and
• the side surface of the protruding portion enclosing the top surface of the protruding portion and having a ring shape, when viewed in a plan view;
• and
• a semiconductor chip on a top surface of the redistribution substrate.

A semiconductor package device, comprising:

• a first semiconductor package, the first semiconductor package including a lower redistribution substrate, a first semiconductor chip on the lower redistribution substrate, and an upper redistribution substrate spaced apart from the first semiconductor chip with the first semiconductor chip being between the upper redistribution substrate and the lower redistribution substrate,
• the lower redistribution substrate including an insulating layer, an under-bump pattern and an outer coupling terminal, the under-bump pattern in the insulating layer and partially exposed to an outside of the insulating layer, and the outer coupling terminal on the under-bump pattern, the under-bump pattern including a body portion and a protruding portion extending from the body portion,
• a thickness of the body portion ranging from 4 μm to 7 μm,
• a thickness of the protruding portion ranging from 1 μm to 3 μm, a level of a lowermost surface of the insulating layer being lower than a level of a lowermost surface of the body portion, and
• the level of a lowermost surface of the insulating layer being higher than a level of a lowermost surface of the protruding portion;
• a connection terminal between the lower redistribution substrate and the first semiconductor chip;
• a conductive pillar between the lower redistribution substrate and the upper redistribution substrate;
• and
• a second semiconductor package on the first semiconductor package.