Interlocked redistribution layer interface for flip-chip integrated circuits
AssigneeNVIDIA Corporation
InventorsYuanjing Jane Li, Chuan Zhang, Jonathon Elliott, Howard Marks
Life of this patent
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Abstract
This disclosure provides an integrated circuit device that includes a RDL that is interlocked with a bump (or “pillar”). The interlocked interface provides the contact RDL-bump interface with increased structural stability that can better withstand the thermal stresses associated with high performance devices IC devices. The interlock structure mitigates crack/delamination that occurs at the RDL-bump interface in large IC chips that are generally subjected to higher stresses during operation.
Claims29
An integrated circuit (IC) device, comprising:
- a semiconductor substrate;
- transistors located over the semiconductor substrate;
- interconnect structures located within an interconnect layer located over the transistors and interconnecting a portion of the transistors together;
- a segmented redistribution layer (RDL) located over the interconnect layer forming RDL contact pads, wherein at least a portion of the RDL contact pads has interlock openings formed therein, the RDL contact pads connected to another portion of the transistors by the interconnector structures;
- and
- a metal connect structure located over each of the RDL contact pads, wherein a portion of the metal connect structure is located within each of the interlock openings of the RDL contact pads to form an interlock structure with the RDL contact pads.
A flip-chip integrated circuit (IC) device, comprising:
- a semiconductor die having transistors and interconnects;
- and
- RDL contact pads located over and connected to at least a portion of the interconnects, the RDL contact pads having interlock openings formed therein that provide a three-dimensional interlock interface with a conductive pillar, a portion of which is located within the interlock openings of the RDL contact pads.
A method of fabricating an integrated circuit (IC) device, comprising:
- patterning a redistribution layer (RDL) located over an IC chip having transistors and interconnects that interconnect the transistors to form RDL contact pads over the IC chip, wherein at least a portion of the RDL contact pads have interlock openings therein;
- placing a conductive metal layer over the RDL contact pads, causing the conductive metal layer to be placed in the interlock openings of the RDL contact pads;
- and
- patterning the conductive metal layer to form a contact pillar over each of the RDL contact pads and an interlock structure between each of the RDL contact pads and the contact pillar.
Dependencies are inferred from the claim text.