Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsYeongkwon KO, Un-Byoung KANG, Jaekyung YOO, Teak Hoon LEE
Life of this patent
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Abstract
A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.
Claims20
A semiconductor package, comprising:
- a package substrate;
- a connection substrate on the package substrate, the connection substrate having a recession on a lower corner of the connection substrate, the recession facing a top surface of the package substrate;
- a semiconductor chip on the connection substrate;
- and
- a plurality of connection terminals connecting the package substrate to the connection substrate such that the recession is laterally spaced apart from the plurality of connection terminals.
A semiconductor package, comprising:
- a package substrate;
- a connection substrate on the package substrate, the connection substrate including a base substrate, a plurality of upper pads on a top surface of the base substrate, a plurality of lower pads on a bottom surface of the base substrate, and a plurality of through vias penetrating the base substrate and connecting the upper pads to the lower pads, the connection substrate including a recession on a lower corner thereof such that a width of the recession is greater than a distance between a sidewall of the connection substrate and an outermost one of the upper pads;
- a chip stack on the connection substrate, the chip stack including a plurality of first semiconductor chips that are vertically stacked;
- a second semiconductor chip spaced apart from the chip stack on the connection substrate;
- a plurality of first connection terminals connecting the connection substrate to the chip stack and connecting the connection substrate to the second semiconductor chip;
- a first under-fill layer filling a gap between the chip stack and the connection substrate and a gap between the second semiconductor chip and the connection substrate;
- a molding layer on the connection substrate, the molding layer covering the chip stack and the second semiconductor chip;
- a plurality of second connection terminals connecting the package substrate to the connection substrate;
- a second under-fill layer filling a gap between the package substrate and the connection substrate;
- and
- a heat radiation structure on the package substrate, the heat radiation structure covering the connection substrate, the chip stack, and the second semiconductor chip.
Dependencies are inferred from the claim text.