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US 2022/0020694 A1Published application
Graphene-Assisted Low-Resistance Interconnect Structures and Methods of Formation Thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShin-Yi Yang, Yu-Chen Chan, Ming-Han Lee, Hai-Ching Chen, Shau-Lin Shue
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Abstract
A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.
Claims20
A semiconductor structure, comprising:
- a first conductive feature disposed in a first dielectric layer;
- a second conductive feature disposed in the first dielectric layer and adjacent to the first conductive feature;
- a graphene layer disposed over the first and the second conductive features;
- and
- a second dielectric layer disposed over the first dielectric layer, wherein sidewalls of the second dielectric layer are defined by the graphene layer.
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A semiconductor structure, comprising:
- a first conductive feature and a second conductive feature disposed in an interlayer dielectric (ILD) layer;
- a first graphene layer disposed over the first conductive feature;
- a second graphene layer disposed over a portion of the second conductive feature;
- an etch-stop layer (ESL) horizontally interposed between the first graphene layer and the second graphene layer, wherein a side surface of the first or the second graphene layer directly contacts a side surface of the ESL;
- and
- a third conductive feature electrically coupled to the second conductive feature, wherein a first side surface of the third conductive feature is separated from the first graphene layer by a portion of the ESL.
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A method, comprising:
- Forming a first conductive feature and a second conductive feature in a first interlayer dielectric (ILD) layer;
- selectively forming a graphene layer over top surfaces of the first and the second conductive features, wherein a top surface of the ILD layer is free of the graphene layer;
- selectively forming an etch-stop layer (ESL) over the top surface of the ILD layer, wherein the top surfaces of the first and the second conductive features are free of the ESL;
- forming a second ILD layer over the first ILD layer;
- etching the second ILD layer to expose the first conductive feature in an opening, wherein the opening is formed between portions of the ESL;
- and
- forming a third conductive feature in the opening.
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Dependencies are inferred from the claim text.