Semiconductor memory device

A semiconductor memory device comprising:

• a substrate including a first area, a second area, and a plurality of block areas, the first area and the second area being arranged in a first direction, each of the block areas being provided to extend in the first direction, and the block areas being arranged in a second direction intersecting the first direction;
• a plurality of insulating members provided to extend in the first direction, the insulating members being respectively disposed at boundary portions between the block areas;
• a plurality of first conductive layers arranged in a third direction intersecting the first and second directions and provided to be separated from one another, the first conductive layers being divided by the insulating members, and the first conductive layers respectively including terraced portions provided not to overlap an upper first conductive layer for each area in which the second area and any one of the block areas overlap;
• a plurality of first pillars provided to penetrate the first conductive layers for each area in which the first area and any one of the block areas overlap;
• a plurality of first contacts respectively provided on the terraced portions for each of the block areas;
• a plurality of second conductive layers respectively coupled to the first contacts above the first conductive layers for each of the block areas;
• and
• a plurality of second contacts provided to extend from a first layer to a second layer and respectively coupled to the second conductive layers for each of the block areas, the first layer being located above the first conductive layers, and the second layer being located between the substrate and the first conductive layers, wherein
• the second area includes a plurality of subareas arranged in the second direction, each of the subareas being disposed across a boundary between two different block areas to overlap a part of each of the two different block areas in the second direction,
• each of the subareas includes a contact area and an insulating area, the contact area including a group of the terraced portions and a group of the first contacts corresponding to two block areas, and the insulating area including a group of the second contacts corresponding to the two block areas, and
• the contact area of an odd-numbered subarea has a structure that is symmetric in the first direction with respect to the contact area of an even-numbered subarea.

A semiconductor memory device comprising:

• a substrate including a first area, a second area, and a plurality of block areas, the first area and the second area being arranged in a first direction, each of the block areas being provided to extend in the first direction, and the block areas being arranged in a second direction intersecting the first direction;
• a plurality of insulating members provided to extend in the first direction, the insulating members being respectively disposed at boundary portions between the block areas;
• a plurality of first conductive layers arranged in a third direction intersecting the first and second directions and provided to be separated from one another, the first conductive layers being divided by the insulating members, and the first conductive layers respectively including terraced portions provided not to overlap an upper first conductive layer for each area in which the second area and any one of the block areas overlap;
• a plurality of first pillars provided to penetrate the first conductive layers for each area in which the first area and any one of the block areas overlap;
• a plurality of first contacts respectively provided on the terraced portions for each of the block areas;
• a plurality of second conductive layers respectively coupled to the first contacts above the first conductive layers for each of the block areas;
• and
• a plurality of second contacts provided to extend from a first layer to a second layer and respectively coupled to the second conductive layers for each of the block areas, the first layer being located above the first conductive layers, and the second layer being located between the substrate and the first conductive layers, wherein
• the second area includes a plurality of subareas arranged in the second direction, each of the subareas being disposed across a boundary between two different block areas to overlap a part of each of the two different block areas in the second direction, and
• each of the subareas includes a first contact area, an insulating area, and a second contact area arranged in the second direction, each of the first contact area and the second contact area including a group of the terraced portions and a group of the first contacts corresponding to one block area, and the insulating area including a group of the second contacts corresponding to two block areas.