Double-side back-end-of-line metallization for pseudo through-silicon via integration

A method of forming a semiconductor device, comprising:

• forming a first metallic layer coupled to a first set of vias
• forming a second metallic layer coupled to a second set of vias;
• forming a plurality of inter-metal dielectrics positioned between the first metallic layer and the second metallic layer;
• forming a first set of metal layers within a first subset of the plurality of inter-metal dielectrics;
• forming a second set of metal layers with a second subset of the plurality of inter-metal dielectrics, wherein the first subset and the second subset are different;
• and
• forming a power delivery network embedded at least partially within the first subset of the plurality of inter-metal dielectrics.

A semiconductor device comprising:

• a first pseudo through-silicon via coupled to a plurality of dielectric layers and comprising a first plurality of metal layers and a second plurality of metal layers;
• a second pseudo through-silicon via coupled to the plurality of dielectric layers and comprising a third plurality of metal layers and a fourth plurality of metal layers;
• a first set of metal layers coupled to a plurality of input and output contacts;
• a second set of metal layers coupled to a power management integrated circuit;
• a plurality of transistors coupled to the first set of metal layers;
• and
• a plurality of voltage sources coupled to the second set of metal layers.