Semiconductor package and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSanghoon JUNG, Young Lyong KIM, Cheolsoo HAN
Life of this patent
Estimating the term…
Abstract
Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate.
Claims21
-10. (canceled)
A semiconductor package, comprising:
- a lower substrate including a conductive line;
- a first semiconductor chip on the lower substrate;
- an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including
- a central part below the first semiconductor chip, and
- an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate;
- and
- a recess region between the central part and the edge part, the recess region defined by a sidewall of the central part, a sidewall of the edge part, and a portion of a top surface of the conductive line.
A semiconductor package, comprising:
- a lower substrate including a conductive line;
- a first semiconductor chip on the lower substrate;
- an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including
- a central part below the first semiconductor chip, and
- an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate;
- and
- a recess region between the central part and the edge part,
- wherein a bottom surface of the recess region is lower the top surface of the lower substrate.
A semiconductor package, comprising:
- a lower substrate including a conductive line;
- an interposer substrate on the lower substrate and electrically connected to the lower substrate through a plurality of bumps;
- a first semiconductor chip on the interposer substrate;
- a plurality of chip stacks on the interposer substrate and isolated from direct contact with each other in a first direction parallel to a top surface of the lower substrate, the first semiconductor chip between the plurality of chip stacks;
- an under-fill layer between the lower substrate and the interposer substrate, the under-fill layer including
- a central part below the interposer substrate, and
- an edge part isolated from direct contact, in the first direction, with the central part;
- and
- a recess region between the central part and the edge part, the recess region defined by a sidewall of the central part, a sidewall of the edge part, and a portion of a top surface of the conductive line in the lower substrate.
Dependencies are inferred from the claim text.