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US 2022/0020652 A1Published application
Electronic chip package having a support and a conductive layer on the support
AssigneeSTMicroelectronics (Tours) SAS
InventorsOlivier ORY, Romain JAILLET
Life of this patent
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Abstract
The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.
Claims20
A method comprising:
- forming a conductive layer on a back surface of a semiconductor wafer;
- coupling a support to the conductive layer;
- forming a plurality of trenches in the semiconductor wafer separating a plurality of chips of the semiconductor wafer from each other;
- and
- forming an insulating casing around the plurality of chips, the conductive layer, and the support, wherein a surface of the support remains exposed from the insulating casing.
2 more elements
A method, comprising:
- forming an electrically conductive layer on a back surface of a semiconductor die of a wafer;
- coupling a support structure to the electrically conductive layer, the electrically conductive layer between the support structure and the semiconductor die;
- forming a conductive structure on a front surface of the semiconductor die, the front surface opposite to the back surface;
- forming a first insulating layer on the semiconductor die and the support structure;
- and
- exposing the conductive structure from the first insulation layer by thinning the first insulation layer.
3 more elements
A method, comprising:
- forming an electrically conductive layer on a back surface of a semiconductor wafer;
- coupling a support structure to the electrically conductive layer, the electrically conductive layer between the support structure and the semiconductor wafer;
- forming a conductive structure on a first region of a front surface of the semiconductor wafer, the front surface opposite to the back surface;
- forming a trench in the semiconductor wafer, the trench surrounding the first region and extending into the support structure, within the trench the semiconductor wafer and the electrically conductive layer having lateral surfaces that are coplanar with one another;
- forming a first insulating layer on the first region of the front surface and in the trench covering the lateral surfaces of the semiconductor wafer and the electrically conductive layer.
2 more elements
Dependencies are inferred from the claim text.