Epitaxial growth of source and drain materials in a complementary field effect transistor (cfet)

A system for performing epitaxial growth to form at least a portion of a source and a drain on multiple levels of a complementary field effect transistor (CFET), the system comprising:

• a memory storing instructions;
• and
• a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
• deposit a first blocking material in a vertical channel of an unfinished CFET structure;
• oxidize silicon at a surface of an upper level of the unfinished CFET structure to provide one or more SiO2 protective layers in the upper level;
• etch away a portion of silicon from a lower level of the unfinished CFET structure to form a lateral recess that is exposed to the vertical channel;
• perform silicon epitaxial growth in the lower level of the unfinished CFET structure including at least a portion of the lateral recess to form the portion of one of the source and the drain;
• and
• after the performing of the silicon epitaxial growth on the lower level:
• deposit a second blocking material in the vertical channel to cover at least a portion of the silicon epitaxial growth in the lower level;
• remove the one or more SiO2 protective layers;
• and
• perform epitaxial growth on the upper level of the unfinished CFET structure to form the portion of another of the source and the drain.

A non-transitory computer readable storage medium comprising stored instructions for performing epitaxial growth to form at least a portion of a source and a drain in multiple levels of a complementary field effect transistor (CFET), the instructions, when executed by a processor, cause the processor to implement operations comprising:

• depositing a first blocking material in a vertical channel of an unfinished CFET structure;
• oxidizing silicon at a surface of an upper level of the unfinished CFET structure to provide one or more SiO2 protective layers in the upper level;
• etching away a portion of silicon from a lower level of the unfinished CFET structure to form a lateral recess that is exposed to the vertical channel;
• performing silicon epitaxial growth in the lower level of the unfinished CFET structure including at least a portion of the lateral recess to form the portion of one of the source and the drain;
• and
• after the performing of the silicon epitaxial growth on the lower level:
• depositing a second blocking material in the vertical channel to cover at least a portion of the silicon epitaxial growth in the lower level;
• removing the one or more SiO2 protective layers;
• and
• performing epitaxial growth on the upper level of the unfinished CFET structure to form the portion of another of the source and the drain.